JPH06132295A - Bipolar transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the overetching of an emitter electrode by forming a lead-out electrode self-alignedly and by eliminating the occurrence of a difference in level of the lead-out electrode on an insulating film formed on a base region. CONSTITUTION:In an emitter opening 20 and a base opening 21, each formed on a part of an insulating film 15 on a base region 12, an emitter lead-out electrode 22a and a base lead-out electrode 22b are formed respectively by self-alignment. With these electrodes used as diffusion sources, an emitter region 13 and a base electrode lead-out region 14 are formed by diffusion in a part of a surface section of the base region 12. After that, an emitter metal electrode 18a is formed so as to cover the emitter lead-out electrode 22a and a base metal electrode 18b is formed so as to cover the base lead-out electrode 22b. By this method, overetching of the emitter electrode can be prevented and a short-circuit fault between the emitter and the base can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing the same, and more particularly to a cutoff frequency ft of 1.
The present invention relates to an electrode structure of a high frequency transistor of 0 GHz or higher and a method for forming the electrode structure.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a plane pattern of a high frequency bipolar transistor having a comb structure used in a discrete device. Figure 4
Shows a conventional example for a part of the cross-sectional structure taken along the line BB in FIG.

Here, 30 is N ⁺ The substrate 31 is an N-type epitaxial layer, and these are collector regions of the NPN transistor. 32 is a P-type base region, 33 is an N-type emitter region, 34 is a thermal oxide film, and 35 is a nitride film.

Reference numeral 36 denotes an emitter extraction electrode which is in contact with the emitter region 33 through an emitter opening provided in a part of the oxide film 34 and the nitride film 35, and is made of polysilicon doped with N-type impurities,
Also serves as an emitter diffusion source. Reference numeral 37 is an emitter electrode made of the first layer aluminum formed on the emitter extraction electrode 36.

Reference numeral 38 is a base electrode made of aluminum of the first layer, which is in contact with the base region 32 through a base opening provided in a part of the oxide film 34 and the nitride film 35.

Reference numeral 39 is an interlayer insulating film formed on the emitter electrode 37 and base electrode 38, and 40 is commonly connected to the emitter electrode 37 through an opening provided in a part of the interlayer insulating film 39. The second-layer aluminum emitter wiring 41 is a second-layer aluminum base wiring commonly connected to the base electrode 38 through an opening provided in a part of the interlayer insulating film 37. The points of improving the performance of the high frequency bipolar transistor having the above-described structure are to improve the cutoff frequency ft and to reduce the noise figure Nf.

In order to improve the cutoff frequency ft, it is necessary to reduce the collector-base capacitance Ccbo and the base resistance rbb, and in order to reduce the noise figure Nf, it is necessary to decrease the base resistance rbb. . The point for reducing the collector-base capacitance Ccbo is to reduce the emitter opening diameter and the base opening diameter by miniaturization.

The point for reducing the base resistance rbb is to reduce the contact resistance of the electrodes and the wiring resistance in addition to reducing the opening distance between the emitter region and the base region by fine processing.

In order to reduce the contact resistance and wiring resistance of the electrodes, an emitter electrode (aluminum electrode in this example) 37 is formed on an emitter extraction electrode (polysilicon electrode) 36 which also serves as an impurity diffusion source. in this case,
The alignment accuracy of the pattern of the polysilicon electrode 36 and the aluminum electrode 37 and the fine processing of the aluminum electrodes 37 and 38 are required.

Conventionally, in a bipolar transistor having an ft of 10 GHz, the contact width of the emitter extraction electrode 36 and the base electrode 38 is 0.7 μm, the opening distance between the emitter and the base is 2.7 μm, the width of the polysilicon electrode 36 and the aluminum. The width of each of the electrodes 37 and 38 is 1.9 μm, and the interval between the aluminum electrodes 37 and 38 is 0.8 μm.

In this case, the polysilicon electrode 36 and the aluminum electrode 37 are formed without alignment accuracy, and the space between the aluminum electrodes 37 and 38 (0.8 μm) is close to the resolution limit of the g-line stepper.

In such a situation, the polysilicon electrode 3
An aluminum film is vapor-deposited on 6 to form an aluminum electrode 37.
If a misalignment between the two patterns occurs during the pattern formation of, the following problems will occur.

FIG. 5 shows an example of a cross-sectional structure after the aluminum film etching step when the resist pattern 42 for the aluminum film etching mask has a misalignment of 0.4 μm with respect to the pattern of the polysilicon electrode 36. ing.

When the resist pattern 42 for the aluminum film etching mask is misaligned with the pattern of the polysilicon electrode 36 in this way, when the aluminum film is patterned to form the aluminum electrode 37, the influence of the unevenness of the underlying layer is exerted. As a result, the polysilicon / emitter extraction electrode 36 is over-etched as indicated by the dotted line A in the figure, and in an extreme case, the emitter contact portion is etched.

Further, due to the presence of the step B of the polysilicon electrode generated by patterning the polysilicon film when forming the polysilicon / emitter extraction electrode 36,
A part C of the aluminum film is not completely etched and remains between the emitter and the base, which may cause a short circuit between the emitter and the base, resulting in a decrease in manufacturing yield.

[0016]

As described above, in the conventional high-frequency bipolar transistor, the polysilicon emitter electrode is over-etched, and in extreme cases, the emitter contact portion is etched. However, there is a problem in that a short circuit between the emitter and the base may occur and the manufacturing yield may be reduced.

The present invention has been made to solve the above problems, and can prevent the over-etching of the emitter electrode and the etching of the emitter contact portion, and can prevent the occurrence of a short circuit between the emitter and the base. It is an object of the present invention to provide a bipolar transistor capable of reducing the number of steps and capable of ultra-high speed operation, and a manufacturing method thereof.

[0018]

In a bipolar transistor of the present invention, an emitter extraction electrode embedded in an emitter opening formed in a part of an insulating film on a base region and this emitter extraction electrode as a diffusion source are used. An emitter region diffused and formed in a part of the surface layer of the base region, a base lead electrode embedded in a base opening formed in a part of an insulating film on the base region, and a base lead A base electrode lead-out region formed by diffusing into a part of a surface layer portion of the base region using an electrode as a diffusion source, an emitter metal electrode formed so as to cover the emitter lead-out electrode, and the base lead-out electrode. A base metal electrode formed to cover the collector region, a collector region formed in contact with the base region, and a collector region formed on the collector region. Characterized by comprising a collector metal electrode formed so as to tact.

The method of manufacturing a bipolar transistor according to the present invention further includes the step of forming a base region of a second conductivity type opposite to the first conductivity type on a part of the main surface of a semiconductor substrate of the first conductivity type. Forming an insulating film on the base region and on the exposed surface of the epitaxial layer, forming an emitter opening and a base opening in the insulating film on the base region, and forming a polysilicon film on the insulating film. And filling the inside of the emitter opening and the inside of the base with the polysilicon, etching back the polysilicon to the upper surface of the insulating film, and polysilicon inside the emitter opening. Implanting first conductivity type impurity ions into the polysilicon and implanting second conductivity type impurity ions into the polysilicon inside the base opening; Forming polysilicon into the emitter opening as an emitter extraction electrode and using the diffusion source as a diffusion source to form an emitter region in a part of the surface layer of the base region; and A step of forming a base extraction electrode by using polysilicon as a base extraction electrode and using the diffusion electrode as a diffusion source to form a base electrode extraction region in a part of the surface layer portion of the base region; A step of forming an emitter electrode so as to cover the electrode and a base electrode so as to cover the base lead electrode.

[0020]

In the bipolar transistor of the present invention, the emitter extraction electrode and the base extraction electrode are buried in the emitter opening and the base opening formed in a part of the insulating film on the base region. An emitter region and a base electrode lead-out region are diffused and formed in a part of the surface layer portion of the base region using the base lead-out electrode as a diffusion source, and an emitter metal electrode is formed to cover the emitter lead-out electrode and the base lead-out electrode A base metal electrode is formed so as to cover it.

Since the extraction electrode is formed by self-alignment, patterning for forming the extraction electrode is unnecessary. This reduces the number of steps, eliminates the misalignment of the emitter and the base, makes the top surface of the extraction electrode and the top surface of the insulating film on the base region flat after the extraction electrode is formed, and allows the extraction electrode to be formed on the insulation film on the base region. No step will occur.

Therefore, since there is no unevenness of the base when patterning the emitter metal electrode and the base metal electrode, over-etching of the emitter electrode and etching of the emitter contact portion do not occur even if misalignment of the metal electrode patterns occurs. In addition, since a part of the metal electrode film remains between the emitter and the base without being etched, a short-circuit defect between the emitter and the base does not occur, and a decrease in manufacturing yield can be prevented.

Further, the method for manufacturing a bipolar transistor of the present invention makes it possible to realize a bipolar transistor having a sufficient performance within a range of a miniaturization technique and a self-alignment technique which can usually be achieved with a small number of steps.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1A to 1E show sectional structures of a semiconductor substrate in a manufacturing process of an NPN transistor according to an embodiment of the present invention.

First, as shown in FIG. 1A, N ⁺ -Type semiconductor substrate (wafer) 10 has an N-type epitaxial layer 11 formed on its surface, and a main surface of this semiconductor substrate 10 (the surface of N-type epitaxial layer 11) is surrounded by a field insulating film (Fig. (Not shown) is formed by a selective oxidation method. Next, a P type base region 12 is formed on the device formation region on the surface of the epitaxial layer 11.

Next, an insulating film 15 is formed on the entire surface of the epitaxial layer 11. As the insulating film 15,
For example, a composite insulating film in which a relatively thin thermal oxide film 16 and a nitride film 17 are laminated is used.

Next, as shown in FIG. 1B, a resist mask having openings surrounding the regions where the emitter is to be formed and the regions where the base is to be extracted is formed, and the nitride film 17 and the oxide film 16 are formed. Are sequentially removed by etching to form an emitter opening 20 and a base opening 21.

The etching in this step is performed by an anisotropic etching method in order to precisely define the dimensions of the transistor. Further, at least two openings are arranged in parallel, and in the case of this embodiment, the size on the reticle is 0.7 μm each, and the distance between the openings is 2.7 μm.

Next, after removing the resist mask, an undoped polysilicon film 2 having a thickness of 500 nm is formed.
2 is deposited to a thickness of 500 nm by the CVD method to fill the emitter opening 20 and the base opening 21 with polysilicon.

Then, as shown in FIG. 1C, the polysilicon film 22 is etched back by using the nitride film 17 as a stopper by a selective polisher, CDE (chemical dry etching) or the like. As a result, the polysilicon 22 and the surface of the nitride film 17 embedded in the emitter opening and the base opening are flattened. Next, N-type impurity (for example, As) ions are implanted into the polysilicon 22 in the emitter opening. In addition, a P-type impurity (for example, B) is added to the polysilicon in the base opening.
Ion implantation.

Next, by performing heat treatment (annealing treatment), as shown in FIG. 1D, the polysilicon 22 in the emitter opening is made into an electrode (emitter extraction electrode 22).
a) and the emitter region 13 as a diffusion source
Are formed by diffusion. Further, by the heat treatment, the polysilicon 22 in the base opening is made into an electrode (base lead electrode 22b), and the base electrode lead region 14 is formed by diffusion using it as a diffusion source. Then, the insulating film 1
A metal film (for example, an aluminum film) 18 is vapor-deposited on the film 5.

Next, as shown in FIG. 1E, the aluminum film 18 is patterned to form an emitter electrode 18a so as to cover the emitter lead electrode 22a and cover the base lead electrode 22b. The base electrode 18b is formed.

Further, a metal film (for example, an aluminum film) is vapor-deposited on the back surface of the N-type substrate 10 which becomes the collector region of the NPN transistor together with the N-type epitaxial layer 11, and is patterned to form a collector electrode (not shown).
To form. FIG. 2 shows an NPN formed as described above.
A part of sectional structure of a transistor is shown.

This NPN transistor has a base region 1
2. The emitter opening 2 formed in a part of the insulating film 15 on
0 and the base opening portion 21 are respectively formed with an emitter lead electrode 22a and a base lead electrode 22b buried therein, and the emitter lead electrode 22a and the base lead electrode 22b are used as diffusion sources, respectively, in a part of a surface layer portion of the base region 12 to form an emitter region. 13 and the base electrode lead-out region 14 are formed by diffusion, an emitter metal electrode 18a is formed so as to cover the emitter lead-out electrode 22a, and a base metal electrode 18b is formed so as to cover the base lead-out electrode 22b.

Since the lead electrodes 22a and 22b are formed by self-alignment, patterning for forming the lead electrodes is unnecessary. As a result, the number of steps is reduced, misalignment between the emitter and the base is eliminated, and after the extraction electrodes are formed, the upper surfaces of the extraction electrodes 22a and 22b and the upper surface of the insulating film 15 on the base region 12 are made flat, and The step of the extraction electrode does not occur on the insulating film 15 of FIG.

Therefore, when patterning the emitter metal electrode 18a and the base metal electrode 18b, since there is no unevenness of the base, over-etching of the emitter electrode or etching of the emitter contact portion occurs even if the metal electrode patterns are misaligned. Does not occur, and a portion of the metal electrode film between the emitter and the base remains without being etched, so that a short-circuit defect between the emitter and the base does not occur, and it is possible to prevent a reduction in manufacturing yield.

Further, the NPN transistor manufacturing method of the above-described embodiment can realize a bipolar transistor having a sufficient performance within a range of the miniaturization technique and the self-alignment technique which can be usually achieved with a small number of steps. .

In the above embodiment, the bipolar transistor is formed as a discrete device, but it is also possible to form it as an output transistor of an ultra high speed integrated circuit by the same method.

In the above embodiment, the vertical bipolar transistor having the substrate and the epitaxial layer as the collector region is formed. However, the present invention is directed to the lateral bipolar transistor in which the collector region faces the emitter region in the base region. It can also be applied to the case of forming a transistor.

[0040]

As described above, according to the present invention, the over-etching of the emitter electrode and the etching of the emitter contact portion can be prevented, the short-circuit defect between the emitter and the base can be prevented, and the number of steps can be reduced. Can be reduced
It is possible to provide a bipolar transistor capable of ultra-high speed operation.

Further, according to the present invention, it is possible to provide a manufacturing method capable of realizing a bipolar transistor capable of operating at an extremely high speed within the range of the miniaturization technique and the self-alignment technique which can usually be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional structure of a semiconductor substrate in each step in a method of manufacturing an NPN transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a part of an NPN transistor formed by the manufacturing method of FIG.

FIG. 3 is a diagram showing a plane pattern of a conventional high frequency bipolar transistor.

FIG. 4 is a cross-sectional view showing a part of the cross-sectional structure along the line BB in FIG.

5 is a diagram showing an example of a cross-sectional structure after an etching process when a pattern misalignment between an aluminum electrode and a polysilicon electrode in FIG. 4 occurs.

[Explanation of symbols]

10 ... N ⁺ Substrate, 11 ... N-type epitaxial layer, 12 ...
Base region, 13 ... Emitter region, 14 ... Base electrode extraction region, 15 ... Insulating film, 16 ... Thermal oxide film, 17 ... Nitride film, 18a ... Emitter metal electrode, 18b ... Base metal electrode, 22 ... Polysilicon film, 22a ... emitter extraction electrode, 22b ... base extraction electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Osawa 1 Komukai-Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Tamagawa Factory, Toshiba Corporation (72) Inventor Masanobu Tsuchiya Komu-Toshi-cho, Kawasaki-shi, Kanagawa No. 1 Incorporation company Toshiba Tamagawa factory

Claims (6)

[Claims] 1. A base region formed on the main surface of a semiconductor substrate, a composite insulating film formed by laminating an oxide film and a nitride film formed on the surface of the base region, and a composite layer on the base region. An emitter extraction electrode made of polysilicon doped with an impurity having a conductivity type opposite to that of the base region and embedded in an emitter opening formed in a part of an insulating film, and the emitter extraction electrode serving as a diffusion source. An emitter region formed by being diffused in a part of the surface layer of the base region, and a base opening formed in a part of the composite insulating film on the base region are embedded and formed to have the same conductivity type as the base region. A base extraction electrode made of polysilicon doped with impurities, and diffused to a part of the surface layer portion of the base region using this base extraction electrode as a diffusion source. A formed base electrode lead region, an emitter metal electrode formed to cover the emitter lead electrode, a base metal electrode formed to cover the base lead electrode, and in contact with the base region. A bipolar transistor comprising a collector region formed and a collector metal electrode formed in contact with the collector region. 2. The vertical bipolar transistor according to claim 1, wherein the bipolar transistor is a vertical bipolar transistor formed so as to include the base region in a part of a surface layer portion of the collector region. Transistor. 3. The vertical bipolar transistor according to claim 1, wherein the bipolar transistor is a horizontal bipolar transistor in which the collector region is formed in the base region so as to face the emitter region. 4. A step of forming a base region of a second conductivity type opposite to the first conductivity type on a part of the main surface of a semiconductor substrate of the first conductivity type, and the base region and the epitaxial layer. Forming an insulating film on the exposed surface; forming an emitter opening and a base opening in the insulating film on the base region; depositing polysilicon on the insulating film to form the inside of the emitter opening; And a step of burying the polysilicon in the inside of the base opening, a step of etching back the polysilicon to the upper surface of the insulating film, and an ion of the first conductivity type impurity in the polysilicon inside the emitter opening. Implanting, implanting ions of the second conductivity type impurity into the polysilicon inside the base opening, and performing heat treatment on the polysilicon inside the emitter opening. As an emitter extraction electrode and using it as a diffusion source to diffusely form an emitter region in a part of the surface layer portion of the base region, and the heat treatment converts the polysilicon inside the base opening into a base extraction electrode. A step of forming an emitter extraction electrode as a step of diffusing and forming a base electrode extraction region in a part of the surface layer portion of the base region using it as a diffusion source; The method comprises: forming an emitter electrode so as to cover the electrode and forming a base electrode so as to cover the base lead electrode; and forming a collector electrode so as to contact the collector region. Manufacturing method of bipolar transistor. 5. The method of manufacturing a bipolar transistor according to claim 4, wherein the collector electrode is formed on the back surface of the main part of the semiconductor substrate. 6. The method of manufacturing a bipolar transistor according to claim 4, further comprising a step of forming the collector region in a part of a surface layer portion of the base region.