JPH0582071B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit wiring method, and more particularly to an integrated circuit wiring method for electrically connecting electrodes and wires provided perpendicularly to a substrate surface.

In a conventional insulated gate field effect transistor, a source/drain region, a channel or gate electrode region, and a channel stopper region are generally arranged in a planar manner. For this reason, although the device integration density has been increased by miniaturizing each region, for example, as the channel length becomes shorter, the short channel effect, which lowers the threshold voltage value of the device, becomes noticeable, and It has become difficult to achieve higher density due to the drop in through voltage. FIG. 1 is a schematic cross-sectional view of a conventionally widely used MOS field effect transistor, in which 1 is a p-type silicon substrate, 2 is a channel stopper region, 3 is a thick field oxide film, 4 is a gate oxide film, and 5 is a impurity implantation layer for controlling threshold voltage, 6
are source/drain regions, 7 is a gate electrode, 8 is an interlayer insulating film, and 9 is a contact hole for forming the source/drain electrodes.

In this way, since the element isolation region, gate region, and source/drain region are arranged in a plane, the effect of high integration will be small unless each of them is miniaturized. However, for example, selective oxidation (LOCOS) using a silicon nitride film as a mask is used for element isolation, which causes oxidation-induced spread (bird's beak) around the field oxide film, which hinders miniaturization. It was coming.

The present inventor has proposed a new semiconductor device structure that improves the drawbacks of this conventional structure. That is, as shown in FIG. 2, the gate electrode and source/drain regions are arranged perpendicular to the substrate surface. FIG. 2 is a schematic perspective sectional view showing an example of this proposed structure in comparison with FIG. 1. In the figure, 21 is a low resistance n-type silicon substrate, 22 is a thick silicon oxide film, and 23 is a high concentration 24 is a conductive polycrystalline silicon gate electrode, 25 is a gate silicon oxide film, 26 is a silicon single crystal region, and 27 is a drain region of a heavily doped n-type diffusion layer.

As described above, the structure of the semiconductor device shown in FIG. 2 is characterized in that the gate electrode and the source/drain regions are provided perpendicularly to the substrate surface. That is, the channel length of a unit transistor is a dimension roughly corresponding to the film thickness of the insulating film, and the channel width is a dimension corresponding to the peripheral length of a single crystal silicon region surrounded by the insulating film. Therefore, the unit dimensions of the transistor can be miniaturized to the extent limited by the photolithography technology used, and the element isolation region is determined only by the mask dimensions for forming the insulating film pattern and does not change during the process. Further, a channel stopper diffusion layer is not required, which is extremely effective in miniaturizing devices. However, since the gate electrode of this structure is formed perpendicularly to the substrate surface, it is difficult to make an electrical connection to the gate electrode. Furthermore, it is generally difficult to electrically connect electrodes and wiring formed perpendicularly to the substrate surface.

An object of the present invention is to provide wiring for integrated circuits that can easily electrically connect electrodes and wiring formed perpendicularly to a substrate and that can increase wiring density. The purpose is to provide a method.

According to the present invention, there is provided a wiring method for an integrated circuit for electrically connecting an electrode or a wiring formed on a side wall of an opening in an insulating film, wherein the insulating film is formed into at least two layers, and each layer A wiring pattern of conductive silicon, metal, or metal silicide is provided between the two, and then the wiring pattern of the insulating film is etched away at a desired portion, and the electrode or wiring is formed on the exposed side wall. A method for wiring an integrated circuit is obtained.

By using the method of the present invention, electrical connections can be easily made to electrodes and wiring formed perpendicular to a plane, and the wiring for this purpose is embedded in an insulating film and formed easily. This has the advantage of making it possible to increase the wiring density.

Next, one embodiment of the present invention will be described with reference to the drawings.
FIGS. 3a to 3f are schematic cross-sectional views showing a part of an integrated circuit formed by wiring n-channel MOS field effect transistors in the order of manufacturing steps.

First, for example, the n of the crystal plane {100} and the specific resistance of 0.01Ωcm
An insulator layer 32 is formed on the surface of the mold silicon substrate 31.
Form to a thickness of 1 μm. This insulator layer 32 is
Although SiO ₂ is suitable, other insulators such as oxides such as alumina, Si ₃ N ₄ , etc. can also be used if selective etching is possible. Next, polycrystalline silicon 33 doped with phosphorus at a high concentration is deposited to a thickness of approximately 0.3 μm using the CVD method, and a wiring for the gate electrode (hereinafter referred to as gate wiring) is formed using ordinary photolithography. When a silicon oxide film 34 is deposited to a thickness of about 1 μm by the CVD method, the image shown in FIG. 3a is obtained.

Next, a resist pattern is formed on the gate wiring pattern using optical exposure technology, etc., and using this as a mask, the CVD oxide film 34, polycrystalline silicon 33,
If the silicon oxide film 32 is etched using a dry etching method so as to have vertical side walls, and then an n-type diffusion layer is formed by specific ion implantation to serve as a source 35, the result shown in FIG. 3B is obtained. After forming a thermal oxide film 36 on the exposed surface of the substrate to insulate the source, polycrystalline silicon 37 having n-type conductivity is deposited by CVD to lower the resistance.
A gate oxide film 38 is provided by thermally oxidizing polycrystalline silicon. Next, when etching is performed in the vertical direction using reactive ion etching or the like without a mask, the gate electrode polycrystalline silicon 37 on the side wall of the insulating film is etched.
Then, the region deposited parallel to the substrate surface is removed by etching, leaving only the gate oxide film 38, resulting in FIG. 3c. After heat treatment in a nitrogen atmosphere to recover from etching damage, for example, dichlorosilane (SiH ₂ Cl ₂ ) is used as a source gas, hydrogen is used as a carrier gas, and hydrogen chloride is added as a 0.02 to 0.5 to hydrogen gas.
When an appropriate amount within the capacity range is added and grown at about 950° C. under a reduced pressure of 50 Torr, the epitaxial film 39 is selectively formed only on the exposed single crystal silicon substrate without growing on the surface of the amorphous insulating film. . During growth, n-type impurities from the substrate are slightly introduced into the epitaxial film, so that the epitaxial silicon layer exhibits low concentration n-type conductivity. Next, a predetermined dose of boron is ion-implanted, and then arsenic, etc.
A channel region 40 and a drain region 41 are respectively formed by shallowly and highly concentrated ion implantation of type impurities. In order to further improve the insulation between the gate electrode and the drain region, a thermal oxide film 42 with a thickness of about 1000 Å is formed on the surface of the epitaxial silicon layer.
FIG. 3d is thus obtained. Deep p like this
DSA is a structure in which a shallow n-type layer is formed within a type layer.
(Diffusion Self-Align), and the threshold voltage value of the "on" and "off" states of the transistor is controlled by the concentration of the p-type layer. this
The DSA structure has been applied to planar transistors and has achieved comparable effects, but in the structure of the present invention, the channel region exists in a direction perpendicular to the substrate, so the entire channel region is controlled to the same threshold voltage value. This difficulty is solved by using this DSA structure.

When a silicon oxide film 43 is deposited as an interlayer insulating film over the entire surface of the substrate by, for example, the CVD method, the result shown in FIG. 3e is obtained. Note that in this figure and the following figure 3f, the thermal oxide film 4
2 has been omitted. Contact holes are formed in the drain and gate electrode regions using ordinary photolithography, and aluminum 44 mixed with about 2% silicon is deposited by magnetron sputtering to form an electrode wiring pattern. After that, heat treatment is performed at approximately 450°C to alloy the contact interface. In this way, FIG. 3f is obtained. In this case, the source electrode is a low-resistance substrate 31, which is commonly used for each element, and it is extremely convenient to set it to a normal ground voltage.

As explained above, in the present invention, it becomes possible to easily make electrical connections to electrodes and wiring formed perpendicular to the substrate surface, and the wiring for making connections can be connected to at least two insulating films. Since it is embedded between the two, there is an advantage that the wiring can be designed with high density. Further, in the present invention, the gate electrode 37 is formed on almost the entire surface of the sidewall, and the impurity is diffused from the diffusion layer source region 35 to the epitaxial film 39 so that the diffusion front is above the lower end of the gate electrode 37. Since the diffusion layer drain region 41 is formed on the surface of the film 39 so that the diffusion front is below the upper end of the gate electrode 37, the source/drain of the MIS transistor and the gate electrode can be reliably overlapped and the threshold can be reached. Just by applying a voltage even slightly higher than the value voltage, even a small drain voltage can be turned on.
Furthermore, although polycrystalline silicon was used as the wiring material in the above embodiment, metals such as Mo, Mo silicide,
Metal silicide such as Ti silicide may also be used.

[Brief explanation of drawings]

FIG. 1 is a sectional view schematically showing a conventional MOS field effect transistor structure, and FIG. 2 is a schematic perspective sectional view showing the structure of the present invention in comparison with FIG. Also, Figure 3 a, b, c, d, e, f are n
This is a schematic diagram showing the main manufacturing steps of a channel MOS transistor in order. ... Impurity layer for threshold voltage control, 6
...source/drain region, 7...gate electrode,
8... Interlayer insulating film, 9... Contact hole, 21,
31... N-type silicon substrate, 22, 32... Thick silicon oxide film, 23, 35... N-type diffusion layer source region, 33... Phosphorus-doped polycrystalline silicon for wiring, 36... Thin silicon oxide film, 24, 37...
...Polycrystalline silicon for gate electrode, 25, 38...
Gate oxide film, 26, 39...n-type epitaxial silicon film, 40...p-type impurity layer, 27, 4
1... N-type diffusion layer drain region, 42... Silicon thermal oxide film, 43... Interlayer insulating film, 44... Aluminum electrode, respectively.

Claims (1)

[Claims] 1. A method for manufacturing an integrated circuit in which an insulating film having an opening is formed on a semiconductor and electrically connected to an electrode or wiring formed on a side wall of the opening, the method comprising forming the insulating film into at least two layers. A wiring pattern is provided between each layer, and then a desired portion of the insulating film and the wiring pattern is etched away, and a first impurity diffusion layer that becomes a source or drain is formed on the exposed semiconductor surface, A gate electrode film is deposited on the entire surface, this electrode film is left only on the side walls by anisotropic etching, a gate insulating film is formed on the side walls of the gate electrode, and a semiconductor film is formed on the exposed semiconductor by selective epitaxial growth. Filling the opening and at the same time diffusing impurities from the diffusion layer into the epitaxial film so that the diffusion front is above the lower end of the gate electrode, and then forming a second impurity diffusion layer to serve as a drain or source on the surface of the grown film. A method of manufacturing an integrated circuit, characterized in that the diffusion front is below the top of a gate electrode.