JP2560376B2 - Method for manufacturing MOS transistor - Google Patents

Description

The present invention relates to a method for manufacturing a MOS transistor having a structure in which gates facing each other on both sides of a channel are provided, and an object is to enable stable formation of a MOS transistor having the structure described above. A semiconductor layer made of a material that is not removed when the substrate is removed by etching is epitaxially grown thereon, a gate insulating layer and a gate electrode are sequentially formed in a predetermined region on the semiconductor layer, and the gate electrode is formed on the semiconductor layer. Overall, the interface with the substrate is insulative, and
A support layer is formed whose back surface has a property of not being removed when the substrate is removed by etching, and the substrate on which the support layer is formed is removed by etching to expose the semiconductor layer. It includes various steps of sequentially forming a second gate insulating layer and a gate electrode in a region corresponding to the gate electrode on the exposed semiconductor layer.

[Industrial applications]

The present invention relates to a MOS transistor, and more particularly to a method for manufacturing a MOS transistor having a structure in which gates facing each other are provided on both sides of a channel.

[Conventional technology]

With the trend toward higher density and higher performance of semiconductor integrated circuits, shortening the channel of MOS transistors forming the integrated circuits is being promoted. LDD (Lightly Doped) is used to solve the problems of hot electrons and the breakdown at the drain region edge that occur with the shortening of the channel.
Drain) structure or DDD (Double Diffused Drain)
A structure has been proposed. Using these structures, it is possible to reduce the channel length to 0.5 μm.

However, the MOS transistors currently in practical use, including the LDD-structured or DDD-structured transistors, are provided with a gate on only one side of the channel layer, and therefore the channel length at which the source-drain current can be controlled by the gate is controlled. The minimum limit is about 0.1 μm, and it is said that transistor operation cannot be obtained with a channel length shorter than this.

[Problems to be solved by the invention]

To overcome this limitation, the MOS structure shown in Fig. 2 has been proposed. (For example, Solid-State Electron
ics, 27 , 8/9 (1985), pp.827-828, Monthly Semiconductor W
Orld, 1986.5, pp.44-49) The transistor of this structure is also called XMOS, and the gate electrodes 2 and 3 facing each other on both sides of the channel 1 are provided.
Is provided. It has been theoretically shown that with this structure, even if the channel length, that is, the distance between the source 4 and the drain 5 is shortened to 0.025 μm, current control by the gate is possible. In FIG. 2, reference numeral 6
Indicates a semiconductor substrate on which a MOS transistor having the above structure is formed.

However, there is no process capable of stably forming the XMOS structure, and it is particularly difficult to form a semiconductor layer having good crystallinity for forming a channel region on the gate insulating film.

It is an object of the present invention to provide a method for stably manufacturing the above XMOS structure transistor.

[Means for solving problems]

The object is to epitaxially grow a semiconductor layer made of a material that is not removed when the substrate is removed by etching on one surface of the substrate, and to form a first gate insulating layer and a first gate electrode on the surface of the semiconductor layer. A step of sequentially forming and covering the gate electrode and the surface of the semiconductor layer exposed from the gate electrode, and at least the interface side in contact with the surface of the gate electrode and the semiconductor layer is insulating.
And a step of forming a support layer having a property that a back surface side facing the interface side is not removed when the substrate is removed by the etching, and a step of forming the support layer of the semiconductor layer by removing the substrate by the etching. Exposing a back surface facing the front surface covered by the support layer, and exposing the exposed back surface of the semiconductor layer to the first gate insulating layer and the first gate electrode This is achieved by the method for manufacturing a MOS transistor according to the present invention, which comprises the step of sequentially forming a second gate insulating layer and a second gate electrode.

[Work]

In the MOS transistor according to the present invention, (1) the substrate can be removed by etching without affecting the semiconductor layer in which the source / drain is formed, so that the XMOS structure can be stably formed (2) channel The epitaxial layer that forms the region is formed before the gate electrode, etc., and has a better crystal quality than the epitaxial layer formed by the conventional technique in which the silicon layer on the gate oxide film is recrystallized by laser beam irradiation. The MOS transistor with excellent characteristics can be obtained because of its high conductivity. (3) Since the semiconductor layer is supported by the supporting layer having an insulating surface, it has a SOI (Silicon on Insulator) structure.
A MOS transistor can be manufactured. (4) By using a SiC thin film as a semiconductor layer, a transistor having a high withstand voltage of the XMOS structure can be manufactured. (5) In the present invention, a step due to the first gate electrode is generated on the semiconductor layer surface. Since the gate electrode and other wiring layers can be formed on a flat surface, the occurrence of obstacles such as disconnection due to steps can be reduced.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of an essential part in a process of an embodiment of the present invention.

Referring to FIG. 1A, for example, a silicon wafer substrate 10
Approximately 2000Å thick semiconductor layer 1 made of SiC (silicon carbide) on top
Epitaxially grow 2. S on silicon wafer
For the epitaxial growth of an iC thin film, an application by the present applicant (Japanese Patent Application Laid-Open No. 62-155512, dated July 10, 1987, Japanese Patent Application No. 62-1).
63370, July 20, 1987, Japanese Patent Application No. 61-167823, Showa 6
The method disclosed on July 18, 1) may be used. In summary, for example, SiHCl ₃ (trichlorosilane) and C ₃ H ₈ (propane) are used as source gases, and low pressure CVD is used.
Epitaxial growth of SiC by reacting the above source gases at a temperature of about 1000 ° C by the chemical vapor deposition method.
An (Epi-SiC) thin film is produced.

In a predetermined region of the Epi-SiC semiconductor layer 12 shown in FIG.
As shown in, the first gate insulating layer 14 and the first gate electrode 16 are sequentially formed. The formation of these is as follows.

First, the semiconductor layer 12 is heated to about 1000 ° C. in a water vapor atmosphere and oxidized to form a SiO ₂ film on its surface. A Poly-Si layer with a thickness of about 3000 Å is deposited on the SiO ₂ film with a thickness of about 300 Å by the well-known polycrystalline silicon (Poly-Si) generation technique using the CVD method or the like. This Poly-Si layer is selectively removed using a known Si etching technique to form the gate electrode 16. Although only the gate insulating layer 14 directly below the gate electrode 16 is left in FIG. 1B, the SiO ₂ film formed as described above is used as the semiconductor layer 12.
It does not matter if you leave it all over.

After the above, as shown in FIG. 1 (c), the gate electrode 16
Forming a resist layer 7 having an opening corresponding to the region containing the impurities, and using the resist layer 7 and the gate electrode 16 as a mask, the exposed semiconductor layer 12 is doped with impurities such as phosphorus (P) or arsenic (As). Source region 18 and drain region 20 are formed by ion implantation. in this case,
The depth of the source region 18 and the drain region 20 is defined by the semiconductor layer
Pour to equal 12 thickness. As described above, when the SiO ₂ film is left on the entire surface of the semiconductor layer 12, ion implantation is performed through this.

After removing the resist layer 7, a support layer 22 having a thickness of several 100 μm is formed on the substrate 10 as shown in FIG. The support layer 22 may be a SiO ₂ layer formed by a known SiO ₂ CVD method. In the figure, the support layer 22 has a thickness of about 3000 Å, for example, an SiO ₂ insulating layer 22-1, and a thickness of about 60.
Poly-Si layer 22-2 of 0 μm and Si ₃ N ₄ layer 22 of about 5000Å thickness
An example of a laminated structure consisting of -3 and -3 is shown.

The SiO ₂ insulating layer 22-1 is provided to electrically separate the semiconductor layer 12 from the Poly-Si layer 22-2. In addition, the Si ₃ N ₄ layer
22-3 is provided for the purpose of protecting the Poly-Si layer 22-2 from an etching solution when the substrate 10 made of a silicon wafer is subsequently removed by etching. Therefore, when the support layer 22 made of SiO ₂ is used as described above, the SiO ₂
The insulating layer 22-1 and the Si ₃ N ₄ layer 22-3 are unnecessary.

As another means of forming the support layer 22, a glass plate made of BPSG (borophosphosilicate glass) and having a thickness of about 500 μm is used,
It is also possible to use a method in which this is superposed on the substrate 10 that has undergone the steps shown in FIG. 1C and then heat-treated to bond it to the substrate 10.

The semiconductor layer 12 has an SOI structure regardless of the method shown in FIG. 1 (d), the method using the SiO ₂ support layer and the BPSG plate.

After the above, the substrate 10 made of a silicon wafer is removed. The results are shown in FIG. 1 (e). In this way,
The Epi-SiC semiconductor layer 12 supported by the support layer 22 is exposed. This figure shows a state in which the upper and lower sides are reversed from those in FIG. 1 (d). To remove the substrate 10, the silicon wafer is
After removing by mechanical polishing to a thickness of about 200 μm, for example, the remaining portion is removed by using a known etching solution composed of a mixed solution of hydrofluoric acid and nitric acid. In this etching, the Si ₃ N ₄ layer 22-3 protects the Poly-Si layer 22-2 from the etching solution.

On the Epi-SiC semiconductor layer 12 exposed as described above, an interlayer insulating layer 24 having a thickness of about 3000Å is formed by using a known SiO ₂ CVD technique, as shown in FIG. 1 (f). After that, the gate electrode 16 is formed by using a known lithographic technique.
The interlayer insulating layer 24 in the region facing the is selectively removed. Then, by performing heat treatment at 1000 ° C. in a water vapor atmosphere, the Epi exposed at the portion where the interlayer insulating layer 24 is removed
A second gate insulating layer 26 made of a SiO ₂ film having a thickness of about 300Å is formed on the SiC semiconductor layer 12.

Next, for example, aluminum (Al) is deposited on the gate insulating layer 26 and the interlayer insulating layer 24 by using a known thin film technique, and this is patterned into a predetermined shape by using a known lithographic technique. In this way, the second gate electrode 28 is formed as shown in FIG. In the figure, reference numerals 30 and 32 are the source region 18 and the drain region.
20 is a source electrode and a drain electrode connected to 20 respectively.

The openings provided in the interlayer insulating layer 24 for connecting these electrodes to the source region 18 and the drain region 20 may be formed simultaneously in the step of providing the openings in the interlayer insulating layer 24 to form the gate insulating layer 26. Alternatively, after forming the gate electrode 28, it may be formed in another lithographic process using a resist mask layer (not shown).

The connection electrode is formed on the first gate electrode 16 as follows, for example. That is, as shown in FIG. 3, it penetrates through the interlayer insulating layer 24, the semiconductor layer 12, and the SiO ₂ layer 14a (formed at the same time as the gate insulating layer 14) on the gate electrode extension 16a which is provided in advance. After forming the opening, a sidewall 34 made of a SiO ₂ film having a thickness of about 3000Å is formed in the opening by using the known SiO ₂ CVD technique and the anisotropic etching technique. After that, a connection electrode 36 made of, for example, Al or polysilicon, which is connected to the gate electrode extension 16a through the opening, is formed.

Interlayer insulating layer 24 and Si to form the opening
A known technique may be used for etching the O ₂ layer 14a. Further, the removal of the Epi-SiC semiconductor layer 12 at this time may be performed by an anisotropic etching method using SiCl ₄ .

According to the method of the present invention described above, the semiconductor layer 12 forming the channel region between the source region 18 and the drain region 20 is epitaxially grown before the formation of the gate electrodes 16 and 28, and therefore has good crystallinity. Therefore, the transistor of the XMOS structure having practical characteristics can be obtained. Further, since the substrate 10 made of a silicon wafer can be selectively removed from the Epi-SiC semiconductor layer 12 in which the source region 18 and the drain region 20 are formed, the back surface thereof can be easily exposed, and the XMOS structure can be formed. It can be stably formed.

Note that the substrate 10 is not limited to a silicon wafer, and other single crystal substrates or amorphous substrates can be used as long as the semiconductor layer 12 can be epitaxially grown. , It does not matter whether it is made of an insulating material.

〔The invention's effect〕

According to the present invention, it is possible to stably manufacture an XMOS structure transistor having practical characteristics expected as an effective method for shortening a channel, and to promote high performance and high density of a semiconductor integrated circuit. There is.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part in a step of an embodiment of the present invention, FIG. 2 is a sectional view of an essential part for explaining a basic structure of an XMOS structure, and FIG. 3 is a connection to a first gate electrode in the present invention. FIG. 6 is a diagram for explaining a method of forming electrodes. In the figure, 7 is a resist layer, 10 is a substrate, 12 is a semiconductor layer, 14 and 26 are gate insulating layers, 14a is a SiO ₂ layer, 16 and 28 are gate electrodes, 16a is a gate electrode extension, 18 is a source region, 20 is a drain region, 22 is a support layer, 22-1 is a SiO ₂ insulating layer, 22-2 is a Poly-Si layer, 22-3 is a Si ₃ N ₄ layer, 24 is an interlayer insulating layer, 30 is a source electrode, 32 Is a drain electrode, 34 is a side wall, and 36 is a connection electrode.

Claims (1)

(57) [Claims] 1. A step of epitaxially growing, on one surface of a substrate, a semiconductor layer made of a material that is not removed when the substrate is removed by etching, and a first gate insulating layer and a first gate electrode on the surface of the semiconductor layer. And a step of sequentially forming the gate electrode and the surface of the semiconductor layer exposed from the gate electrode, and at least the interface side in contact with the surface of the gate electrode and the semiconductor layer is insulative, and the interface Forming a support layer having a property that the back side opposite to the side is not removed when the substrate is removed by the etching, and the support layer of the semiconductor layer is formed by removing the substrate by the etching. Exposing a back surface of the semiconductor layer facing the front surface, the first gate insulating layer and the first gate insulating layer being provided on the back surface of the exposed semiconductor layer; A method of manufacturing a MOS transistor, comprising a step of sequentially forming a second gate insulating layer facing a gate electrode and a second gate electrode.