JPS6119118A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPS6119118A
JPS6119118A JP13963984A JP13963984A JPS6119118A JP S6119118 A JPS6119118 A JP S6119118A JP 13963984 A JP13963984 A JP 13963984A JP 13963984 A JP13963984 A JP 13963984A JP S6119118 A JPS6119118 A JP S6119118A
Authority
JP
Japan
Prior art keywords
insulating film
substrate
film
silicon
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13963984A
Other languages
Japanese (ja)
Inventor
Naoki Kasai
直記 笠井
Nobuhiro Endo
遠藤 伸裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13963984A priority Critical patent/JPS6119118A/en
Publication of JPS6119118A publication Critical patent/JPS6119118A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent generation of crystal defects on an epitaxially-grown Si layer and to enable to manufacture a flat semiconductor substrate by a method wherein an Si nitride film and then a polycrystalline or amorphous Si film are formed on the side wall of an insulating film before an epitaxial growing method is performed. CONSTITUTION:An SiO2 insulating film pattern 12 having a vertical cross-section is formed on a P type single crystal Si substrate 11, and then an Si nitride film 13 is deposited thereon. Then, after a film 13 is formed on the side wall only of an insulating film by performing a reactive ion etching method, amorphous Si 14 is deposited. Subsequently, an etching is performed on the Si 14 located on the insulating film and the substrate 11, and then Si 16 is selectively overetched. Then, Si 16 is selectively epitaxially grown on the surface only of the substrate 11. According to the above-mentioned method of manufacture, no crystal defects are generated on the epitaxially grown layer 16, and a flat semiconductor substrate can be obtained.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、表面に絶縁膜パターンが形成された単結晶シ
リコン層に選択的にシリコンエピタキシャル層を成長さ
せるような半導体基板の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor substrate in which a silicon epitaxial layer is selectively grown on a single crystal silicon layer having an insulating film pattern formed on its surface.

(従来技術とその問題点) 近来、半導体デバイスにおける能動素子間の分離方法は
選択酸化法にかわる微細で深い素子分離領域を形成可能
な新しい技術が要求されている。
(Prior Art and its Problems) Recently, as a method for isolating active elements in semiconductor devices, a new technique that can form fine and deep element isolation regions is required in place of the selective oxidation method.

微細で深い素子分離領域を形成する方法としてたとえば
、遠藤により電子通信学会技術研究報告5SD83−5
2の39 ページから45ページに「選択エピタキシャ
ル成長による素子分離」と題して発表された論文におい
ては、第1図(a)K示すようにシリコン単結晶基板1
上にあらかじめ素子分離領域となるシリコン酸化膜パタ
ーン2を形成し1次いで絶縁膜側壁にのみシリコン窒化
膜あるいは多結晶シリコン薄膜3を形成し1次いで絶縁
膜パターン2上には堆積することなく露出したシリコン
基板領域にのみシリコンエピタキシャル層4を成長させ
ると、絶縁膜側壁がシリコン窒化膜の場合には、第1図
(b)に示したように8102パターン2に接してファ
セット5が形成されるため凹凸のある基板となシ、絶縁
膜側壁に多結晶シリコンを形成した場合には、第1図(
C)に示したように平坦な基板が得られることが示され
ている。
For example, as a method for forming fine and deep element isolation regions, Endo describes
In the paper published on pages 39 to 45 of 2 entitled "Element Isolation by Selective Epitaxial Growth", as shown in Figure 1(a)K, a silicon single crystal substrate 1
A silicon oxide film pattern 2 that will serve as an element isolation region is formed on the insulating film pattern 2 in advance, and then a silicon nitride film or a polycrystalline silicon thin film 3 is formed only on the side walls of the insulating film, and then exposed without being deposited on the insulating film pattern 2. When the silicon epitaxial layer 4 is grown only in the silicon substrate region, if the sidewall of the insulating film is a silicon nitride film, a facet 5 is formed in contact with the 8102 pattern 2 as shown in FIG. 1(b). If the substrate is uneven and polycrystalline silicon is formed on the sidewall of the insulating film, the pattern shown in Figure 1 (
It has been shown that a flat substrate can be obtained as shown in C).

しかしながら、このような構造を有する半導体基板上に
たとえばMOS)ランジスタを形成すると、絶縁膜パタ
ーン側壁にシリコン窒化膜を用いた場合に社前記エピタ
キシャル成長シリコン層は結晶欠陥のない優れた単結晶
となる反面、絶縁膜パターンに接して形成されるファセ
ット5による段差が、たとえばゲート電極形成の際の障
害となる。また、絶縁膜側壁に多結晶もしくは非晶質シ
リコンを用いた場合には平坦な基板が得られる反面エピ
タキシャル成長シリコン層4は絶縁膜側壁近傍に結晶欠
陥が生じたり、SiO□パターンが変形する場合もあり
、その結果t  p”  接合のリーク電流の発生や絶
縁耐圧の低下といった問題を生じ、製造歩留りを低下さ
せた。
However, when a transistor (for example, MOS) is formed on a semiconductor substrate having such a structure, the epitaxially grown silicon layer becomes an excellent single crystal without crystal defects when a silicon nitride film is used on the sidewall of the insulating film pattern. The step caused by the facet 5 formed in contact with the insulating film pattern becomes an obstacle when forming a gate electrode, for example. Furthermore, if polycrystalline or amorphous silicon is used for the sidewalls of the insulating film, a flat substrate can be obtained, but the epitaxially grown silicon layer 4 may have crystal defects near the sidewalls of the insulating film or deformation of the SiO□ pattern. As a result, problems such as the occurrence of leakage current in the tp'' junction and a decrease in dielectric strength voltage occurred, resulting in a decrease in manufacturing yield.

(発明の目的) 本発明は、このような従来の欠点を除去せしめて、エピ
タキシャル成長シリコン層に結晶欠陥が生ずることがな
くしかも平坦な半導体基板の製造方法を提供することに
ある。
(Object of the Invention) An object of the present invention is to eliminate such conventional drawbacks and provide a method for manufacturing a flat semiconductor substrate in which no crystal defects occur in an epitaxially grown silicon layer.

(発明の構成) 本発明は、少くとも表面にシリコン単結晶層を備えた基
板上に絶縁膜を形成し1次いで該絶縁膜の所望の部分に
開口部を設け1次いで前記開口部にのみ選択的にシリコ
ン膜をエピタキシャル成長する半導体基板の製造方法に
おいて、エピタキシャル成長する前に絶縁膜側壁にシリ
コン窒化膜つづいて多結晶あるいは非晶質シリコン薄膜
を形成することを特徴とした半導体基板の製造方法を与
えるものである。
(Structure of the Invention) The present invention includes forming an insulating film on a substrate having at least a silicon single crystal layer on the surface, first providing an opening in a desired portion of the insulating film, and then selecting only the opening. Provided is a method for manufacturing a semiconductor substrate in which a silicon film is grown epitaxially, the method comprising forming a silicon nitride film followed by a polycrystalline or amorphous silicon thin film on the sidewall of an insulating film before epitaxial growth. It is something.

(構成の詳細々説明) 本発明は、上述の構成をとることにより従来技術の問題
点を解決した。絶縁膜側壁にシリコン窒化膜層を形成す
ることでエピタキシャル成長したシリコン層とSiO2
パターンとの界面特性が向上し、結晶欠陥のないエピタ
キシャル成長シリコン層が得られる。また、多結晶もし
くは非晶質シリコン層をさらにシリコン窒化膜上に設け
ることで平坦な半導体基板が得られる。
(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration. The epitaxially grown silicon layer and SiO2 are formed by forming a silicon nitride film layer on the side walls of the insulating film.
The interface characteristics with the pattern are improved, and an epitaxially grown silicon layer without crystal defects can be obtained. Further, by further providing a polycrystalline or amorphous silicon layer on the silicon nitride film, a flat semiconductor substrate can be obtained.

(実施例) 以下本発明の実施例について図面を参照して詳細に説明
する。
(Example) Examples of the present invention will be described in detail below with reference to the drawings.

第2図は本発明の詳細な説明するために1主な製造工程
における基板の断面を順を追って示した模式図である0 面方位(100)のp型巣結晶シリコン基板11(比抵
抗15Ω・cm)に熱酸化により厚さ2μmのシリコン
酸化膜を形成した後、通常の写真蝕刻技術と反応性イオ
ンエツチング法によって素子分離領域となる垂直断面を
もつ8 i 02絶縁膜ノ(ターン12を形成し、次い
で減圧CVD法によりシリコン窒化膜13を厚さ100
0^堆積すると第2図(a)の断面形状の基板を得る。
FIG. 2 is a schematic diagram sequentially showing the cross section of the substrate in 1 main manufacturing process in order to explain the present invention in detail.・After forming a silicon oxide film with a thickness of 2 μm on the 8 i 02 insulating film (turn 12) with a vertical cross section that will become the element isolation region by using ordinary photolithography and reactive ion etching, Then, a silicon nitride film 13 is formed to a thickness of 100 mm by low pressure CVD method.
0^ When deposited, a substrate having the cross-sectional shape shown in FIG. 2(a) is obtained.

次いで反応性イオンエツチング法で絶縁膜上およびシリ
コン基板上のシリコン窒化膜をエツチングし、絶縁膜側
壁にのみシリコン窒化膜層を形成しに後、プラズマCV
D法によシアモルファスシリコ刈4を厚さ700^堆積
すると第2図(b)の断面形状の基板を得る0 次いで1反応性イオンエツチング法よりS 1C14ガ
スを用いて絶縁膜上に堆積したアモルファスシリコンお
よびシリコン基板上のアモルファスシリコンをエツチン
グし、つづいて基板シリコン面15を1000λ程度オ
ーバーエツチングすると第2図(C1を得る。
Next, the silicon nitride film on the insulating film and the silicon substrate is etched using a reactive ion etching method to form a silicon nitride film layer only on the side walls of the insulating film.
By depositing shear amorphous silico-cutting 4 to a thickness of 700^ by the D method, a substrate having the cross-sectional shape shown in FIG. When the amorphous silicon and the amorphous silicon on the silicon substrate are etched, and then the substrate silicon surface 15 is over-etched by about 1000λ, the pattern shown in FIG. 2 (C1) is obtained.

次に31H2CJ2とH2から構成されるガス系にMC
Iを約IVO1%程度加え、950℃の温度でシリコン
基板表面にのみ選択的忙シリコンをエピタキシャル成長
させ、堆積シリコン16の厚さが2μmのとき第2図(
b)の構造を得る。
Next, add MC to the gas system consisting of 31H2CJ2 and H2.
Approximately 1% IVO was added to selectively epitaxially grow silicon only on the surface of the silicon substrate at a temperature of 950°C, and when the thickness of the deposited silicon 16 was 2 μm, as shown in Fig. 2 (
Obtain the structure of b).

次いで950℃の酸素歩囲気中で厚さ200k のゲー
ト酸化膜17を形成し、イオン注入によりホウ素を加速
エネルギー30KeVで注入量1×1012C〆と加速
エネルギー100keVで2X1012cm−2の二重
注入する。
Next, a gate oxide film 17 with a thickness of 200K is formed in an oxygen atmosphere at 950 DEG C., and boron is doubly implanted by ion implantation at an implantation amount of 1.times.10@12 C at an acceleration energy of 30 keV and at a dose of 2.times.10@12 cm@-2 at an acceleration energy of 100 keV.

次いで減圧CVD法によシボリシリコン膜を厚さ500
0^堆積し、写真蝕刻法とドライエツチング法によシグ
ート電稜18を形成し1次いでセルファラインでヒ素を
加速エネルギー150keVで510  c+n  イ
オン注入し、ソース・ドレイン層19を形成し、ポリシ
リコンゲート電極18にリンを拡散すると第2図(e)
を得るー 次いで、電子ビーム蒸着法によりアルミニウム膜を1μ
m堆積し、写真蝕刻法とドライエツチング法により配線
21を形成する。次いで/クツシベーション膜22を堆
積しコンタクトをあけると第2図(f)に示すようなn
チャネルMO8FE’l”が得られる。
Next, a shibori silicon film was formed to a thickness of 500 mm using the low pressure CVD method.
0^ is deposited, a Sigurt electrode ridge 18 is formed by photolithography and dry etching, and then 510 c+n ions are implanted with arsenic at an acceleration energy of 150 keV using a self-line, a source/drain layer 19 is formed, and a polysilicon gate is formed. When phosphorus is diffused into the electrode 18, Fig. 2(e)
- Next, a 1 μm aluminum film is deposited by electron beam evaporation.
The wiring 21 is formed by photolithography and dry etching. Next, a /custivation film 22 is deposited and a contact is made, resulting in an N layer as shown in FIG. 2(f).
Channel MO8FE'l'' is obtained.

(発明の効果) 本実施例から得られたnチャネルMOSト−yンジスタ
は従来方法から得られたものに比べてゲート耐圧に優れ
、p−n  接合リーク電流も減少し。
(Effects of the Invention) The n-channel MOS transistor obtained from this example has superior gate breakdown voltage and reduced p-n junction leakage current compared to those obtained from the conventional method.

製造歩留りが向上した。Manufacturing yield improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(alは従来方法による選択エピタキシャル成長
する前の基板の構造を模式的に示した断面図である。 第1図(b)は従来方法の8i02パターン側壁に窒化
膜層を形成しシリコン選択エピタキシャル成長した後の
基板構造を模式的に示した断面図である。 第1図(C)は従来方法のSiO2パターン側壁に多結
晶あるいは非晶質シリコン層形成しシリコン選択エピタ
キシャル成長した後の基板構造を模式的に示した断面図
である。 第2図(a)から(f)は本発明の実施例におけるnチ
ャネルMO8FETの製造工程を順を追って示した断面
模式図である。 図において。 1.11・・・・・・(100)シリコン単結晶基板、
2゜12−・・5i02絶縁膜パターン、3・・・・・
・シリコン窒化膜あるいは多結晶シリコン膜、4.16
・・−・エピタキシャル成長シリコン層、5 ・・・フ
ァセット、13 ・・・シリコン窒化膜、14・・・・
・アモルファスシリコンJIIE、15・・・−オーバ
ーエラチンフサれたシリコン基板表面、17 ・・ゲー
ト酸化膜、線アルミニウムg、22・・・・・パッシベ
ーション膜第1図 (C)
Figure 1 (al) is a cross-sectional view schematically showing the structure of the substrate before selective epitaxial growth is performed using the conventional method. FIG. 1(C) is a cross-sectional view schematically showing the substrate structure after epitaxial growth. FIG. 2 is a schematic cross-sectional view. FIGS. 2(a) to 2(f) are schematic cross-sectional views sequentially showing the manufacturing process of an n-channel MO8FET in an example of the present invention. In the figures: 1. 11...(100) silicon single crystal substrate,
2゜12-...5i02 insulation film pattern, 3...
・Silicon nitride film or polycrystalline silicon film, 4.16
...Epitaxially grown silicon layer, 5...Facet, 13...Silicon nitride film, 14...
・Amorphous silicon JIIE, 15...-Silicon substrate surface with over-elatin, 17...Gate oxide film, line aluminum g, 22...Passivation film Fig. 1 (C)

Claims (1)

【特許請求の範囲】[Claims]  少なくとも表面にシリコン単結晶を備えた基板上に絶
縁膜を形成し、次いで該絶縁膜の所望の部分に開口部を
設け、次いで前記開口部にのみ選択的にシリコン膜をエ
ピタキシャル成長する半導体基板の製造方法において、
エピタキシャル成長する前に絶縁膜側壁にシリコン窒化
膜つづいて多結晶あるいは非晶質シリコン薄膜を形成す
ることを特徴とした半導体基板の製造方法。
Manufacturing a semiconductor substrate by forming an insulating film on a substrate having a silicon single crystal on at least the surface, then providing an opening in a desired portion of the insulating film, and then epitaxially growing a silicon film selectively only in the opening. In the method,
1. A method of manufacturing a semiconductor substrate, which comprises forming a silicon nitride film followed by a polycrystalline or amorphous silicon thin film on the sidewall of an insulating film before epitaxial growth.
JP13963984A 1984-07-05 1984-07-05 Manufacture of semiconductor substrate Pending JPS6119118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13963984A JPS6119118A (en) 1984-07-05 1984-07-05 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13963984A JPS6119118A (en) 1984-07-05 1984-07-05 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS6119118A true JPS6119118A (en) 1986-01-28

Family

ID=15249958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13963984A Pending JPS6119118A (en) 1984-07-05 1984-07-05 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS6119118A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358921A (en) * 1986-08-29 1988-03-14 Fujitsu Ltd Manufacture of semiconductor device
JPS63292644A (en) * 1987-05-26 1988-11-29 Fujitsu Ltd Manufacture of semiconductor device
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
JP2013258257A (en) * 2012-06-12 2013-12-26 Takehide Shirato Semiconductor device manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6358921A (en) * 1986-08-29 1988-03-14 Fujitsu Ltd Manufacture of semiconductor device
JPS63292644A (en) * 1987-05-26 1988-11-29 Fujitsu Ltd Manufacture of semiconductor device
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
JP2013258257A (en) * 2012-06-12 2013-12-26 Takehide Shirato Semiconductor device manufacturing method

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