JPS6358921A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6358921A
JPS6358921A JP20424986A JP20424986A JPS6358921A JP S6358921 A JPS6358921 A JP S6358921A JP 20424986 A JP20424986 A JP 20424986A JP 20424986 A JP20424986 A JP 20424986A JP S6358921 A JPS6358921 A JP S6358921A
Authority
JP
Japan
Prior art keywords
film
semiconductor
insulating film
region
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20424986A
Other languages
Japanese (ja)
Inventor
Masayuki Takeda
正行 武田
Junji Sakurai
櫻井 潤治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20424986A priority Critical patent/JPS6358921A/en
Publication of JPS6358921A publication Critical patent/JPS6358921A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form semiconductor region having a high concentration in to eliminate a leakage current by containing an interface, and one conductivity type impurity in an insulating film around a recess region so as to diffuse the impurity at the edge of a semiconductor layer before selective growth of the layer is carried out. CONSTITUTION:SiO2 film parts 2 are formed to make a recess region 3, a polycrystalline silicon film 10 is grown thereon to form an SiO2 film 10', and vertically etched by RIE method to allow the film 10' to remain only on the surfaces the region 3. Then, an n-type silicon layer 4 is selectively grown by epitaxial growth, with reaction gas in which phosphine is added to trichlorosilane (SiHCl3) of main ingredient, and the recess region is filled by the growth to flatten the surface. Phosphorus is diffused from the film 10' at the time of growth, and an n<+> type silicon regions 41 are formed on the side surfaces in contact with the film 10'. Thus, since the regions 41 of high concentration are formed on the side surfaces of insulating film element separating bands, the production of an inverted layer due to a crystal defect is suppressed, and the generation of a leakage current is also suppressed.

Description

【発明の詳細な説明】 目既要] 予め、絶縁膜素子分離帯を形成した後、半導体基板上の
凹部領域に、素子形成用の半導体層を選択成長する形成
法であって、半導体層を選択成長する際、−導電型不純
物が半導体層の周囲に拡散するように、予め、凹部領域
の周囲の絶縁膜、または、絶縁膜全面に一導電型不純物
を含有させておく。そうすると、素子分離帯の側壁界面
でのリーク電流がなくなって、半導体素子の品質が向上
する。
[Detailed Description of the Invention] Summary] A formation method in which a semiconductor layer for forming an element is selectively grown in a recessed region on a semiconductor substrate after an insulating film element isolation band is formed in advance. During selective growth, impurities of one conductivity type are contained in the insulating film around the recessed region or the entire surface of the insulating film in advance so that the -conductivity type impurities are diffused around the semiconductor layer. This eliminates leakage current at the sidewall interface of the device isolation band, improving the quality of the semiconductor device.

〔産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に、絶縁分離
帯間に半導体層を選択的にエビタキシャル成長して、そ
の半導体層に素子を形成する製造方法の改善に関する。
[Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to an improvement in a manufacturing method in which a semiconductor layer is selectively grown epitaxially between insulating separation bands and an element is formed in the semiconductor layer. .

ICやLSIなどの半導体装置においては、半導体基板
上に多数の半導体素子(セル)が設けられており、これ
らの半導体素子を電気的に分離するための、素子分離帯
が形成されるが、その素子分離帯は出来るだけ精度良く
微細に形成することが望ましい。従って、微細な素子分
離帯を設ける各種の製法が提案されているが、そのよう
な構造の半導体装置は高品質化について十分に留意しな
ければならない。
In semiconductor devices such as ICs and LSIs, a large number of semiconductor elements (cells) are provided on a semiconductor substrate, and element isolation bands are formed to electrically isolate these semiconductor elements. It is desirable to form the element isolation band as precisely and finely as possible. Therefore, various manufacturing methods have been proposed in which fine isolation bands are provided, but sufficient attention must be paid to improving the quality of semiconductor devices having such structures.

[従来の技術] 従前より、絶縁膜による素子分離帯の形成法として、I
 OP (Isolation Of Po1ysil
icon)法やLOCO3法が著名であるが、この方法
は表面に凹凸が生じ易くて、且つ、素子分離帯を微細化
し難いために、最近、IC−?’LSIの高集積化に通
した形成方法として、半導体基板上に絶縁膜を形成し、
その絶縁膜をパターンニングして素子領域部分の絶縁膜
を除去して凹部領域とし、その凹部領域に半導体層を選
択的にエピタキシャル成長して、その半導体層に素子を
形成する製造方法が考案されている。
[Prior Art] Conventionally, I
OP (Isolation of Polysil)
The IC-? 'As a formation method for achieving high integration of LSI, an insulating film is formed on a semiconductor substrate,
A manufacturing method has been devised in which the insulating film is patterned to remove the insulating film in the element region to form a recessed region, and a semiconductor layer is selectively epitaxially grown in the recessed region to form an element in the semiconductor layer. There is.

このような製造方法の工程順断面図を第3図(a)〜(
C)に示しているが、その概要を説明すると、まず、同
図ta+に示すように、p型シリコン基板1上に素子分
離帯としての酸化シリコン(SiO2)膜2を被着し、
リソグラフィ技術を用いてパターンニングして凹部領域
3を形成する。次いで、同図(′b)に示すように、n
型9937層4を選択エピタキシャル成長する。しかる
後、同図(C)に示すように、n型9937層4に公知
の製法でMO3半専半導体5を形成する。
Figures 3(a)-(
To explain the outline of the process, first, as shown in ta+ in the same figure, a silicon oxide (SiO2) film 2 as an element isolation band is deposited on a p-type silicon substrate 1,
The concave region 3 is formed by patterning using lithography technology. Next, as shown in the same figure ('b), n
Type 9937 layer 4 is selectively epitaxially grown. Thereafter, as shown in FIG. 4C, an MO3 semi-conducting semiconductor 5 is formed on the n-type 9937 layer 4 by a known manufacturing method.

第4図(al、 (blはかくして形成した半導体装置
とその問題点を説明するための図を示し、同図(alは
断面図、同図(′b)は平面図で、同図(b)のAA’
A面が同図falである。図において、1はp型シリコ
ン基板、2は5i02膜からなる絶縁膜素子分離帯。
Figures 4 (al and bl) show diagrams for explaining the thus formed semiconductor device and its problems; )'s AA'
Side A is fal in the same figure. In the figure, 1 is a p-type silicon substrate, and 2 is an insulating film element isolation band made of a 5i02 film.

4はn型シリコン層、51はp型のソース領域およびド
レイン領域、52はゲート絶縁膜、53はゲート電極を
示している。
4 is an n-type silicon layer, 51 is a p-type source region and drain region, 52 is a gate insulating film, and 53 is a gate electrode.

即ち、本製造方法によれば、素子分離帯2が微細に形成
できると共に、素子を形成するためのn型9937層4
(ウェル領域)を浅く形成できて、ICが一層高集積化
されるもので、構造はLOCO8法と類似であるが、バ
ーズビークの発生等がなく、分離帯幅を1μm程度に微
細化できる利点のある方法である。
That is, according to the present manufacturing method, the device isolation band 2 can be formed finely, and the n-type 9937 layer 4 for forming the device can be formed finely.
The structure is similar to the LOCO8 method, but the advantage is that it does not cause bird's beaks and the separation band width can be miniaturized to about 1 μm. There is a certain method.

[発明が解決しようとする問題点〕 ところで、上記の形成方法において、SiO□膜2(絶
縁膜分離帯)をリソグラフィ技術によってパターンニン
グして凹部領域3を形成し、次いで、凹部領域にn型9
937層4を選択エピタキシャル成長すると、5i02
膜2との界面のn型9937層4に結晶欠陥が発生する
。これは、n型9937層4と5i02膜2と接触する
面には結晶欠陥が発生し易いこと、且つ、エツチングの
ために、5i02膜2の側面(凹部領域の側面)にエツ
チング残渣等の不純物が付着すること等に原因があり、
容易にn型シリコン層が界面でp型に反転して反転層が
形成される。
[Problems to be Solved by the Invention] By the way, in the above formation method, the SiO□ film 2 (insulating film separation band) is patterned by lithography technology to form the recessed region 3, and then an n-type film is formed in the recessed region. 9
When 937 layer 4 is selectively epitaxially grown, 5i02
Crystal defects occur in the n-type 9937 layer 4 at the interface with the film 2. This is because crystal defects are likely to occur on the surface in contact with the n-type 9937 layer 4 and the 5i02 film 2, and because of etching, impurities such as etching residues may be present on the side surfaces of the 5i02 film 2 (side surfaces of the recessed region). This is caused by the adhesion of
The n-type silicon layer is easily inverted to the p-type at the interface, forming an inversion layer.

そのため、n型9937層4に投げた半導体素子にリー
ク電流(漏洩電流)が多く生じて、素子特性を悪化させ
る欠点がある。実験データによれば、第4図(blにお
けるA面、B面(幅0.5um程度)からのリーク電流
の発注が特に多い結果が得られている。
Therefore, there is a drawback that a large amount of leakage current occurs in the semiconductor element placed on the n-type 9937 layer 4, which deteriorates the element characteristics. According to the experimental data, leakage current from the A side and the B side (width about 0.5 um) in FIG. 4 (bl) is particularly high.

本発明は、このような問題点を抑制して、半導体装置を
高品質化させる半導体装置の製造方法を提案するもので
ある。
The present invention proposes a method for manufacturing a semiconductor device that suppresses such problems and improves the quality of the semiconductor device.

[問題点を解決するための手段1 その目的は、半導体基板上に絶縁膜を形成し、該絶縁膜
を選択的に除去して、前記半導体基板が底面に露出した
凹部領域を形成する工程、次いで、全面に一導電型不純
物を含む多結晶半導体膜を被着し、次に、該多結晶半導
体膜を熱酸化して酸化半4体膜に変成する工程、次いで
、該酸化半導体膜を垂直に異方性エツチングして、前記
凹部領域の側面のみに該酸化半導体膜を残存させる工程
、次いで、前記凹部領域に一導電型半導体層を選択的に
エピタキシャル成長する工程が含まれる半導体装置の製
造方法によって解決される。
[Means for Solving the Problem 1] The purpose is to form an insulating film on a semiconductor substrate and selectively remove the insulating film to form a recessed region in which the semiconductor substrate is exposed at the bottom; Next, a polycrystalline semiconductor film containing impurities of one conductivity type is deposited on the entire surface, and then the polycrystalline semiconductor film is thermally oxidized to transform it into an oxide semi-quaternary film. A method for manufacturing a semiconductor device, comprising the steps of etching the oxide semiconductor film anisotropically to leave the oxide semiconductor film only on the side surfaces of the recessed region, and then selectively epitaxially growing a semiconductor layer of one conductivity type in the recessed region. solved by.

また、半導体基板上に絶縁膜を形成し、該絶縁膜に一導
電型不純物を含有させる工程、次いで、該絶縁膜を選択
的に除去して凹部領域を形成する工程、次いで、前記凹
部領域に一導電型半導体層を選択的にエピタキシャル成
長する工程が含まれる半導体装置の製造方法によっても
解決される。
Further, a step of forming an insulating film on a semiconductor substrate and incorporating an impurity of one conductivity type into the insulating film, then a step of selectively removing the insulating film to form a recessed region, and then a step of forming a recessed region in the recessed region. The problem can also be solved by a method of manufacturing a semiconductor device that includes a step of selectively epitaxially growing a semiconductor layer of one conductivity type.

[作用] 即ち、本発明は、半導体層を選択成長する前に、−導電
型不純物が半導体層の縁部に拡散するよう、予め、凹部
領域の周囲の絶縁膜、または、絶縁膜全面に一導電型不
純物を含有させておく。
[Operation] That is, in the present invention, before the semiconductor layer is selectively grown, the insulating film around the recessed region or the entire surface of the insulating film is injected in advance so that the -conductivity type impurity is diffused to the edge of the semiconductor layer. A conductivity type impurity is contained.

そうすれば、界面で高濃度な半導体領域(チャネルカッ
ト領域)が形成される。従って、側面でのリーク電流が
なくなって、高品質化される。
In this way, a highly concentrated semiconductor region (channel cut region) is formed at the interface. Therefore, leakage current at the side surfaces is eliminated, resulting in high quality.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(a)〜(e)は本発明にかかる製造方法の工程
順断面図を示している。まず、同図(a)に示すように
、p型シリコン基板1を1050〜1100℃の高温度
で数百分間熱酸化して、膜厚1μm程度のSiO□膜2
を生成し、次いで、リソグラフィ技術によって5i02
膜2をパターンニングして凹部領域3を形成する。この
5i02膜2のパターンニングは、レジスト膜(図示せ
ず)をマスクとして、四弗化炭素(CF4)またはトリ
フロロメタン(CHF3)ガスを反応ガスとしたりアク
ティブイオンエツチング(RIE)でおこなう。
FIGS. 1(a) to 1(e) show step-by-step sectional views of the manufacturing method according to the present invention. First, as shown in the same figure (a), a p-type silicon substrate 1 is thermally oxidized at a high temperature of 1050 to 1100°C for several hundred minutes, and a SiO□ film 2 with a thickness of about 1 μm is formed.
and then 5i02 by lithography technique
The membrane 2 is patterned to form the recessed regions 3. Patterning of the 5i02 film 2 is performed by active ion etching (RIE) using carbon tetrafluoride (CF4) or trifluoromethane (CHF3) gas as a reactive gas using a resist film (not shown) as a mask.

次いで、第1図(b)に示すように、その上面に、減圧
化学気相成長(減圧CVD)法によって膜厚1000〜
1500人の多結晶シリコン膜10を成長する。
Next, as shown in FIG. 1(b), a film with a thickness of 1,000 to 1,000 mm is formed on the top surface by low pressure chemical vapor deposition (low pressure CVD).
1,500 polycrystalline silicon films 10 are grown.

このCVD法は、モノシラン(SiHa)とホスフィン
(PH3)とをソースとして、700〜750℃で熱分
解させて、比抵抗0.01Ω国程度の多結晶シリコン膜
を被着する方法である。
This CVD method uses monosilane (SiHa) and phosphine (PH3) as sources and thermally decomposes them at 700 to 750° C. to deposit a polycrystalline silicon film having a specific resistance of about 0.01Ω.

次いで、第1図(C)に示すように、950℃、数十分
間の熱酸化処理をおこない、多結晶シリコン膜を膜厚2
000〜2500 AのSi○2膜10゛に変成し、更
に、垂直にRIEをおこなって、凹部領域3の側面にの
み5i02膜10’を残存させる。
Next, as shown in FIG. 1(C), thermal oxidation treatment was performed at 950°C for several minutes to reduce the polycrystalline silicon film to a thickness of 2.
The 5i02 film 10' is transformed into a SiO2 film 10' having a thickness of 000 to 2500 A, and RIE is performed vertically to leave the 5i02 film 10' only on the side surfaces of the recessed region 3.

次いで、第1図(d)に示すように、トリクロールシラ
ン(Si HCl3 )と主体とし、ホスフィンを附加
した反応ガスを用いて、950〜1000℃の温度で約
30分間熱分解させて、n型9937層4を選択エピタ
キシャル成長し、凹部領域を埋没させて、表面を平坦に
する。この成長時に、上記の5i02膜101から燐が
n型9937層4に拡散し、SiO2膜10“と接する
側面にn“型シリコン領域41が形成される。しかし、
この場合、燐の拡散のための温度1時間が不足する時に
は、更に、窒素ガス中の高温度(950〜1000℃)
で40〜60分熱処理を追加しても良い。
Next, as shown in FIG. 1(d), thermal decomposition was performed at a temperature of 950 to 1000° C. for about 30 minutes using a reaction gas containing trichlorosilane (Si HCl3) as the main component and phosphine added to give n. A type 9937 layer 4 is selectively grown epitaxially to fill the recessed regions and flatten the surface. During this growth, phosphorus diffuses from the 5i02 film 101 into the n-type 9937 layer 4, and an n"-type silicon region 41 is formed on the side surface in contact with the SiO2 film 10". but,
In this case, when the temperature for diffusion of phosphorus is insufficient for 1 hour, the high temperature (950-1000℃) in nitrogen gas is added.
You may add heat treatment for 40 to 60 minutes.

次いで、第1図(e)に示すように、公知の製法にてn
型9937層4にMOS半導体素子5を形成する。
Next, as shown in FIG. 1(e), n
A MOS semiconductor element 5 is formed on the mold 9937 layer 4.

このような形成方法を採れば、絶縁膜素子分離帯の側面
に高濃度な領域41(チャネルカット領域)が形成され
るため、結晶欠陥による反転層の生成、率いては、リー
ク電流の発生が抑制されて、MOS半導体素子5の素子
特性が安定し、ICを高品質化することができる。
If such a formation method is adopted, a highly concentrated region 41 (channel cut region) is formed on the side surface of the insulating film element isolation band, which prevents the formation of an inversion layer due to crystal defects and, in turn, the generation of leakage current. As a result, the device characteristics of the MOS semiconductor device 5 are stabilized, and the quality of the IC can be improved.

また、第2図(a)〜(C1は本発明にかかる他の製造
方法の工程順断面図を示しており、本例ではまず、同図
(alに示すように、p型シリコン基板1を1050〜
1100℃の高温度で数百分間熱酸化して、膜厚1μm
程度の5i02膜2を生成し、その5i02膜2にイオ
ン注入法によって、燐(又は砒素)イオンを注入する。
In addition, FIGS. 2(a) to (C1) show step-by-step sectional views of another manufacturing method according to the present invention, and in this example, first, as shown in the same figure (al), a p-type silicon substrate 1 is 1050~
Thermal oxidation is performed at a high temperature of 1100℃ for several hundred minutes, resulting in a film thickness of 1μm.
A 5i02 film 2 of about 100% is produced, and phosphorus (or arsenic) ions are implanted into the 5i02 film 2 by an ion implantation method.

次いで、第2図(blに示すように、リソグラフィ技術
によって5i02膜2をパターンニングして凹部領域3
を形成する。この5i02膜2のパターンニングは、上
記例における第1図(a)の工程と同様にしておこなう
Next, as shown in FIG.
form. The patterning of this 5i02 film 2 is carried out in the same manner as the step shown in FIG. 1(a) in the above example.

次いで、第2図(C)に示すように、n型9937層4
を選択エピタキシャル成長して、凹部領域を埋没させる
。この成長時に、上記の5i02膜2から燐がn型99
37層4に拡散し、5i02膜2と接する側面にn+型
シリコン領域41が形成される。
Next, as shown in FIG. 2(C), an n-type 9937 layer 4 is formed.
selective epitaxial growth to fill the recessed regions. During this growth, phosphorus is transferred from the 5i02 film 2 to n-type 99
37 layer 4, and an n+ type silicon region 41 is formed on the side surface in contact with the 5i02 film 2.

説明の詳細は略するが、この工程も上記例における第1
図(d)の工程と同様である。
Although the details of the explanation are omitted, this step is also the same as the first step in the above example.
This process is similar to the process shown in Figure (d).

次は図示していないが、第1図(e)と同様に、公知の
製法でn型9937層4にMO3半導体素子5を形成す
る。
Next, although not shown, the MO3 semiconductor element 5 is formed on the n-type 9937 layer 4 by a known manufacturing method, similar to FIG. 1(e).

このような形成方法によっても、絶縁膜素子分離帯の側
面に高濃度な領域41(チャネルカット領域)が形成さ
れる。且つ、第2図に示す製造方法において、5i02
膜2に燐をイオン注入する代わりに、シリコン基板1表
面に予め燐を注入しておいて、5i02膜の熱酸化時に
、燐を5i02膜2に含有させる方法も考えられる。
Also by such a formation method, a high concentration region 41 (channel cut region) is formed on the side surface of the insulating film element isolation band. Moreover, in the manufacturing method shown in FIG. 2, 5i02
Instead of ion-implanting phosphorus into the film 2, a method may also be considered in which phosphorus is implanted into the surface of the silicon substrate 1 in advance and phosphorus is contained in the 5i02 film 2 during thermal oxidation of the 5i02 film.

尚、これらの第2図で説明した製造方法は工程が簡単化
される利点のあるものである。
Incidentally, the manufacturing method explained in FIG. 2 has the advantage of simplifying the process.

[発明の効果] 以上の説明から明らかなように、本発明によれば、絶縁
膜素子分離帯の側面にチャネルカット領域が形成され、
絶縁膜界面におけるリーク電流が減少して、ICの品質
を向上させることができるものである。
[Effects of the Invention] As is clear from the above description, according to the present invention, a channel cut region is formed on the side surface of the insulating film element isolation band,
Leakage current at the insulating film interface is reduced, and the quality of the IC can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は本発明にかかる製造方法の工程
順断面図、 第2図ta)〜(C)は本発明にかかる他の製造方法の
工程順断面図、 第3図は(a)〜(C)は従来の製造方法の工程順断面
図、第4図16)、 (b)は従来の問題点を説明する
図である。 図において、 lはp型シリコン領域、 2は5i02膜(絶縁膜素子分離帯)、3は凹部領域、 4はn型シリコン層、 5はMO3半導体素子、 10は多結晶シリコン膜、 10′は5i02膜、 41はn“型シリコン領域 を示している。 3E!JiP4′を培。 第1図 5 MOS景) 滞発9耳l;か勺・3公應す1未1のL序7>虚畔面図
第1図 3凹部丑懺′ ント巧ン(ヲMtミI−9・シイ亡コη用メロJ對わる
。っ工゛1呵匠+ylンdうtl旨コL?13凹鐸頒緘
。 4シワフシ層 、/ むn袈皮方3’ly+工蛭F11ぐ断旬m第3図 53ゲニトt& 従#e+KIE臭5iteRT>tn 第4ti(l
1(a) to (e) are step-by-step cross-sectional views of a manufacturing method according to the present invention, FIG. 2 ta) to (C) are step-by-step cross-sectional views of another manufacturing method according to the present invention, and FIG. (a) to (C) are step-by-step cross-sectional views of a conventional manufacturing method, and FIG. 4(b) is a diagram illustrating the problems of the conventional method. In the figure, l is a p-type silicon region, 2 is a 5i02 film (insulating film element isolation band), 3 is a recessed region, 4 is an n-type silicon layer, 5 is an MO3 semiconductor element, 10 is a polycrystalline silicon film, and 10' is a 5i02 film, 41 indicates the n" type silicon region. 3E! Cultivate JiP4'. Figure 1 5 MOS view) Illustrated drawing Figure 1 Figure 3 Recessed part 4 wrinkle layers, / mun kepi 3'ly + hiru F11 gu danjun m Figure 3

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に絶縁膜を形成し、該絶縁膜を選択
的に除去して、前記半導体基板が底面に露出した凹部領
域を形成する工程、 次いで、全面に一導電型不純物を含む多結晶半導体膜を
被着し、次に、該多結晶半導体膜を熱酸化して酸化半導
体膜に変成する工程、 次いで、該酸化半導体膜を垂直に異方性エッチングして
、前記凹部領域の側面のみに該酸化半導体膜を残存させ
る工程、 次いで、前記凹部領域に一導電型半導体層を選択的にエ
ピタキシャル成長する工程が含まれてなることを特徴と
する半導体装置の製造方法。
(1) forming an insulating film on a semiconductor substrate and selectively removing the insulating film to form a recessed region in which the semiconductor substrate is exposed at the bottom; Depositing a crystalline semiconductor film, and then thermally oxidizing the polycrystalline semiconductor film to transform it into an oxide semiconductor film; Next, vertically anisotropically etching the oxide semiconductor film to remove side surfaces of the recessed region. A method for manufacturing a semiconductor device, comprising: a step of leaving the oxide semiconductor film only in the recessed region; and a step of selectively epitaxially growing a semiconductor layer of one conductivity type in the recessed region.
(2)半導体基板上に絶縁膜を形成し、該絶縁膜に一導
電型不純物を含有させる工程、 次いで、該絶縁膜を選択的に除去して凹部領域を形成す
る工程、 次いで、前記凹部領域に一導電型半導体層を選択的にエ
ピタキシャル成長する工程が含まれてなることを特徴と
する半導体装置の製造方法。
(2) a step of forming an insulating film on a semiconductor substrate and incorporating an impurity of one conductivity type into the insulating film; then, a step of selectively removing the insulating film to form a recessed region; then, a step of forming a recessed region; 1. A method of manufacturing a semiconductor device, comprising the step of selectively epitaxially growing a semiconductor layer of one conductivity type.
JP20424986A 1986-08-29 1986-08-29 Manufacture of semiconductor device Pending JPS6358921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20424986A JPS6358921A (en) 1986-08-29 1986-08-29 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20424986A JPS6358921A (en) 1986-08-29 1986-08-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6358921A true JPS6358921A (en) 1988-03-14

Family

ID=16487323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20424986A Pending JPS6358921A (en) 1986-08-29 1986-08-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6358921A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5073516A (en) * 1991-02-28 1991-12-17 Texas Instruments Incorporated Selective epitaxial growth process flow for semiconductor technologies
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160475A (en) * 1974-11-22 1976-05-26 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKITAINOSEIZOHO
JPS6060716A (en) * 1983-09-14 1985-04-08 Nec Corp Manufacture of semiconductor substrate
JPS60214425A (en) * 1984-04-11 1985-10-26 Matsushita Electric Ind Co Ltd Manufacture of magnetic recording medium
JPS6119118A (en) * 1984-07-05 1986-01-28 Nec Corp Manufacture of semiconductor substrate
JPS62219916A (en) * 1986-03-20 1987-09-28 Sharp Corp Manufacture of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160475A (en) * 1974-11-22 1976-05-26 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKITAINOSEIZOHO
JPS6060716A (en) * 1983-09-14 1985-04-08 Nec Corp Manufacture of semiconductor substrate
JPS60214425A (en) * 1984-04-11 1985-10-26 Matsushita Electric Ind Co Ltd Manufacture of magnetic recording medium
JPS6119118A (en) * 1984-07-05 1986-01-28 Nec Corp Manufacture of semiconductor substrate
JPS62219916A (en) * 1986-03-20 1987-09-28 Sharp Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5073516A (en) * 1991-02-28 1991-12-17 Texas Instruments Incorporated Selective epitaxial growth process flow for semiconductor technologies

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