JPS594048A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain excellent element isolation characteristic and element characteristic by forming the stripe or grid type element isolation insulating film at the bottom part of recess formed in the predetermined element forming region of semiconductor substrate. CONSTITUTION:An SiO2 film 22 is formed on the surface of an Si substrate 21 and a recess part 24 is also formed with a resist pattern 23 used as the mask. Next, an SiO2 film 25 for element isolation is formed on the surface. Then, stripe or grid type SiO2 film pattern is formed at the bottom of recess part using a resist pattern 26 as the mask. After removing the pattern 26, silicon Si 27 adding impurity in the conductivity type opposing to that of the substrate is formed deeper than the recess 24 on the entire part of substrate. Then, a fluid substance film 28 is applied to the entire part in order to make flat the surface. The layer 27 is buried in flat in the recess 24 by uniformly etching the film 28 and film 27. After removing the exposed film 22, the layer 27 is single-crystallized. At this time, the n-channel MOSFETQn is formed on the layer 27 while the p-channel MOSFETQp on the substrate region adjacent thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to improvements in element isolation technology.

[Technical background of the invention and its problems]

Conventionally, complementary MO8 (hereinafter referred to as CMO8) conductor devices require electrical separation of n-channel MO8 transistors and p-channel MO8) transistors formed on the same substrate, for example, when these elements are separated by more than 1 Oltm. They are formed apart. For this reason, ultra-LS aiming for high integration
I was extremely inconvenient. As an attempt to improve this drawback, there is a technique of forming a deep trench around the MOS transistor and surrounding the trench by filling it with an insulating material such as oxide. This technique will be explained below using FIG. 1. For example, a resist 12 is coated on the N-type silicon substrate 11, and the resist 12 is patterned by ordinary photolithography (8). Using the no-f turned resist 12 as a mask, n-channel M etching is performed using reactive ion etching (hereinafter referred to as RIg) technology.
O8) Etch the periphery of the region where the transistor is to be formed to form a groove 13 of ~1.5 μm and depth of ~5 μm (b). After removing the resist 12, a silicon oxide film 14, for example, is deposited using the CVD technique, and then photorenost, for example, is applied thereon as a fluid material film 15 (e). Next, under the conditions that the etching rate of this fluid material film 15 and the silicon oxide film 14 are equal, RIE technology is used to etch the silicon substrate 11.
flatten the surface (d). Furthermore, n-channel MOS
Using a photoresist 16 patterned by ordinary photolithography as a mask, p-type impurity ions are implanted into a region where a transistor is to be formed to form a p-well 17 (e). From then on, follow the normal steps.
A channel MO8) transistor Qn is formed adjacent to this, and a p-channel MO8) transistor Qp is formed (
f).

However, in this method, the groove 14 in which the insulator for element isolation is buried is formed by RIE technology, so it is extremely difficult to reduce the width to 1 μm or less, and the area taken up by the element isolation region is large. This is extremely inconvenient for VLSIs aiming for high integration and high density. Also, groove 1
Since the width of the groove 4 is narrow compared to its depth, the insulator cannot be completely buried in the groove, resulting in formation of cavities and a low F of the reliability of the element. Furthermore, in the CMO8 semiconductor device, there are disadvantages such as a latch-up phenomenon easily occurring between the n-channel MO3FFT and the p-channel MO8FFT. It is an object of the present invention to provide a method for manufacturing a semiconductor device that achieves high integration and also makes it possible to obtain excellent device isolation characteristics and device characteristics.

[Summary of the invention]

In the present invention, four portions are formed in a predetermined region of a semiconductor substrate where an element is to be formed, and an insulating film for element isolation is formed on the inner surface of the recess. At this time, the element isolation insulating film is
They are arranged on the entire surface of the 11I surface, and in a stripe or grid pattern on the bottom surface.

Then, a semiconductor layer is buried in this recess, and desired elements are respectively formed in this semiconductor layer region and a substrate region separated from this by the insulating film. Since the element isolation insulating film formed on the bottom surface can be easily realized with an extremely thin thickness of 1 μm or less by, for example, thermal oxidation, the width of the element isolation region is narrow, and therefore high integration can be achieved. In addition, by forming the insulating film on the bottom surface of the four parts of the substrate in a striped or lattice shape, it becomes easy to single-crystallize the semiconductor layer in the recessed part by laser annealing, for example, and latch-up is easily caused in CMO8 semiconductor devices. Since the phenomenon can be effectively prevented, device characteristics and external characteristics are improved.

[Embodiments of the invention]

Examples of the present invention will be described below with reference to FIGS. 2(,) to (h). First, a 5102 film 22 is formed on the surface of an n-type silicon substrate 21 by thermal oxidation or CVD, and is obtained by photolithography. ? After etching, the silicon substrate 2 is etched to a depth of approximately 5 μm by anisotropic dry etching, such as RIE, to form four parts 24.
(a). After removing the i4 turn 23, thermal oxidation or carbon is applied to the silicon surface of the exposed recess 24.
850282 for element isolation of 5ooo1 by VD method
5 (b). Next, a resist layer was formed using a conventional photolithography method (iJ?). Using the turn 26 as a mask, the 5I02 film 25 on the bottom of the recess is etched with, for example, ammonium fluoride solution to form a striped or grid-like 5I film on the bottom.
02 film/lean is formed (c). At this time, the pattern seen from the top becomes as shown in FIG. 3(,) or (b). After removing the resist layer and turns 26, silicon 27 doped with an impurity of the conductivity type opposite to that of the substrate is formed on the entire surface using Evitacal vapor phase epitaxy or CVD to a thickness equal to the depth of the recess 24 (d). In the figure, 271 means a part where a single crystal is grown by epitaxial vapor phase growth, and 272 means a part where polycrystalline silicon is formed.

In all cases where the CVD method is used, polycrystalline silicon will be formed. Thereafter, a photoresist, for example, is applied to the entire surface as the fluid material film 28 to make the surface flat. At this time, if it is not flattened with one application,
Apply it again to the entire surface and make sure it is completely flat. Next, the fluid material film 28 and the silicon layer 27 are uniformly etched by the aN&A dry etching method under conditions that the etching rate is the same for the silicon layer 27.
is buried flatly in the recess 24 (f). After etching and removing the 5102 film 22 exposed on the silicon substrate surface, the silicon substrate surface is laser annealed to single-crystallize the embedded silicon hazy using the single-crystal region 271 as a nucleus (g ). Thus n
A p-type silicon layer 27 separated from the type silicon substrate 21 by a thin 5I02 film 25 is obtained. In addition, when a polycrystalline silicon layer is formed by the CVD method, there are no single crystal nuclei as described above, but there are cases where the portion in contact with the single crystal substrate 21 is not a nucleus, or a silicon layer is formed. Single crystallization is possible. Thereafter, by a normal device forming process, for example, an n-channel MOS transistor Qn is formed on the p-type silicon layer 27, and a p-channel MOS transistor Q is formed on the n-type substrate region adjacent thereto (h).

According to this embodiment, since element isolation is performed using the 5IO2 film formed on the inner surface of the four parts formed on the substrate surface, the area occupied by the element isolation region is much smaller than in the conventional case. High integration is achieved. In addition, since the 5I02 film is arranged in a stripe or lattice pattern on the bottom of the recess, the silicon layer buried in the recess can be easily made into a single crystal, forming a high-quality silicon layer to improve device characteristics. can be achieved. Furthermore, when a CMO8 semiconductor device was constructed, it was left on the bottom of the recess. The latch-up phenomenon is effectively prevented by the 5102 film.

Note that in the above embodiment, an insulating film is formed on the entire side surface of the recessed part of the silicon substrate, and an insulating film is formed on the bottom surface in a striped or lattice pattern).
9 It is possible to suppress the characteristic carbo-chiazo phenomenon observed in CMO8 semiconductor devices, but latch-up can be further suppressed by ion-implanting impurities of the opposite conductivity type to the substrate into the bottom surfaces of these four parts, for example at the stage shown in FIG. 2(c). Suppression of the phenomenon becomes more effective. In addition, in the above embodiment, 8
Although a 102 film was formed and separated from the substrate, the same effect can be obtained by using an 813N4 film produced by CVD or direct nitridation as an element isolation insulating film with only slight changes in the subsequent steps.

[Brief explanation of drawings]

Figures 1(&) to (f) are schematic diagrams for explaining the manufacturing process of a conventional element isolation CMO8 semiconductor device, and Figures 2(a) to (
h) is a diagram for explaining the manufacturing process of a CMO8 semiconductor device according to an embodiment of the present invention, and FIG. It is a diagram. 21... N-type silicon substrate, 22... 8102 film,
23...Resist pattern, 24...Concave portion, 25.
...5in2 film (insulating film for element isolation), 26... resist pattern, 27... p-type silicon layer, 2B...
Fluid substance membrane. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 1 14 14 Figure 2 Figure 2 F7

Claims (5)

[Claims] (1) A step of forming a recess in a predetermined element formation area of a semiconductor substrate, and a step of disposing an insulating film for element isolation in a stripe or lattice shape on the entire side surface of the recess and the bottom surface of the recess, A step of selectively embedding a semiconductor layer in the recessed portion where the insulating film is provided, and a step of forming a desired element in the buried semiconductor layer region and a substrate region separated from this by the insulating film. A method for manufacturing a semiconductor device, comprising: (2) The process of forming the recesses is an anisotropic dryer. A method of manufacturing a semiconductor device as claimed in claim 1, according to Pat. (3) The insulating film for element isolation is made by thermal oxidation or CVD.
10. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a 102 film. (4) The process of selectively embedding a semiconductor layer in the recesses involves depositing a thicker semiconductor layer on the entire surface of the substrate by epitaxial growth or CVD to close the recesses, and covering the surface of the deposited semiconductor layer with a fluid material. A process of flattening with a film, a process of uniformly etching the fluid material film and the semiconductor layer at the same etching rate, leaving the semiconductor layer only in the recessed parts, and annealing and crystallization of the remaining semiconductor layer. A method for manufacturing a semiconductor device according to claim 1, comprising the steps of: (5) The semiconductor layer buried in the recess has a conductivity type opposite to that of the substrate, and the elements formed in this buried semiconductor layer region and other substrate regions are MOSs with different conduction channels.
A method for manufacturing a semiconductor device according to claim 1, which is a transistor.