JPS5986263A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form the insulation isolating region of an MOS transistor in which the displacement from the designing size of the width of a diffused layer is suppressed to the minimum limit without producing an irregularity on the surface of a substrate by etching by utilizing the difference of the etching velocity. CONSTITUTION:An oxidized film 23 is formed on the surface of a substrate 21, and a photoresist 24 is patterned on a region to become a diffused layer region. The film 23 of the region to become a field region and the substrate 21 are etched to remove the photoresist 24, and the film 23 is formed in a groove. A nitrided film 28 is grown by a reduced pressure CVD method and a nitrided film 29 is grown by a plasma CVD method, the resist 24 is patterned, and the films 28, 29 are removed by isotropic plasma etching. Since the etching in a horizontal direction precedes in a vertical direction, the nitrided films are completely buried into the grooves without an irregularity. A polycrystalline silicon 26 to become a gate electrode and wirings is grown, an ion implantation is performed to form source and drain 27.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect semiconductor device using polycrystalline silicon for a gate electrode.

Conventionally, insulation isolation of M2S) transistors has been carried out by a method of isolation using a buried lobe pancreas formed by selective oxidation. The case where the above selective oxidation method is applied to the manufacturing process of MO8IC is shown in FIGS. 1(a) to 1(d).

FIG. 1(a) After forming an oxide film 13 of about 500 A on the surface layer of the two-handed conductor substrate 11, a nitride film 12 of about 1500 A is grown to form an insulating isolation region (hereinafter referred to as a field region). , the photoresist 14 is patterned so that the nitride film 12 in the region is removed.

FIG. 1(b) Second nitride film 12@: After etching,
In the field region, in order to prevent the formation of a channel, an impurity 15 having the same conductivity type as the semiconductor substrate is ion-implanted to serve as a channel striker.

FIG. 1(C): After removing the photoresist 14, selective oxidation is performed for a long time to form a thick oxide film in the field region. At this time, at the end of the nitride film 12, the oxide film is formed even below the nitride film 12, and the width of the diffusion layer becomes significantly narrower than the designed value. The penetration of this oxide film increases as the thickness of the field Fv film becomes thicker, and when the thickness of the oxide film in the field part is 1 μm, the penetration of the oxide film is 0.8 to 1 μm.
．． It even reaches 0 μm.

No. 11 bacteria/d): Nitride film 12 and oxide film 13 below it
is etched to form W oxide, which is to become a gate oxide film, in the diffusion layer region. After that, polycrystalline silicon 16 that will become the gate electrodes, poles, and wiring is grown, patterned, and using the gate polycrystalline silicon as a mask,
A source and a drain 17 are formed by ion-implanting impurity of a reverse conduction type onto the substrate using a self-alignment line. Thereafter, a phosphorus glass layer as an interlayer film is grown using a normal manufacturing method, holes are drilled into the contact at predetermined positions, and metal contacts are formed.
Apply J.

As mentioned above, in the conventional insulation isolation method between transistors, it is necessary to design the diffusion layer width wide in advance in consideration of the sandwiching of the diffusion layer, making it difficult to achieve high integration of MO8 integrated circuits. It is.

Furthermore, if the width of the diffusion layer is narrow at the time of design, the width of the diffusion layer is significantly narrowed due to the selective oxidation, and the characteristics of the transistor are not deteriorated at all due to the narrow channel effect.

An object of the present invention is to provide a method for manufacturing a field effect semiconductor device using polycrystalline silicon for a gate electrode.

When forming the insulation isolation and regions between transistors,
1. It is possible to form an insulating isolation region of a MOS transistor without creating irregularities on the surface of a semiconductor substrate and minimizing deviation from the design dimension of the diffusion layer width,
The present invention provides a high-density MUS integrated circuit having a diffusion layer width of 2 μm or less, which cannot be formed using conventional techniques.

The structure of the present invention for achieving the above object will be explained next.

In the present invention, when performing insulation isolation between transistors (MUD), the semiconductor substrate in a region to be a field region is vertically etched by anisotropic dry etching, and a trench of a predetermined depth is excavated in the trench. After growing a low-pressure CVD nitride film to the depth of the groove, a plasma CVD method was applied.
A thin nitride film is grown on the surface of the nitride film, and a photoresist is patterned using a high-precision Yuri exposure device so that the nitride film in the groove is not etched.

After that, the nitride film on the diffusion layer is etched using the difference in etching speed between the nitride film formed by the low pressure CVD method and the nitride film formed by the plasma CVD method in isotropic plasma etching. At the same time, a nitride film is buried in the trench without a difference in level from the diffusion layer region and without unevenness in the field region. By using the above series of technologies, the difference 1 between the design value of the diffusion layer width and the diffusion layer width on the semiconductor substrate is minimized, and the MOS
) A method for manufacturing a semiconductor device, which is characterized in that it does not easily cause the narrow channel effect of transistors due to a reduction in the width of the diffusion layer when transistors are highly integrated, and enables a highly integrated MO8 integrated circuit. It is.

A detailed explanation of this 7 with reference to FIG. 2 is as follows.

No. zr'a (a): Approximately 1000λ on the surface of the semiconductor substrate 21
An oxide film 23 of about 100 mL is formed and patterned so that it remains on the photoresist 24 over the region to become the diffusion layer region.

1!2 (b) = After etching the oxide film 23vf in the region to become the field region, the semiconductor substrate 21 is vertically etched to a predetermined depth by anisotropic plasma etching. Thereafter, while leaving the photoresist i on the diffusion layer region, impurity ions of the same conductivity type as the semiconductor substrate 21 are implanted into the field region as a channel resist.

FIG. 2(C): Photoresist on the diffusion layer) 24 is removed, and an oxide film of about 500λ is formed in the groove.

At this time, since additional oxidation occurs on the diffusion layer, the oxide film becomes thick, but this serves to protect the diffusion layer with a thick oxide film when plasma etching of the nitride film is performed later. Thereafter, a nitride film 28 having the same thickness as the depth of the groove is grown by low pressure CVD. Further, a nitride film 29 is formed on the surface of the nitride film 28 by plasma CVD.
grow thin.

Next, the photoresist 24 is patterned to remove the nitride film 28.2 Ft on the diffusion layer by isotropic plasma etching. This (turning) is performed so that the resist edge is 0.2 to 0.3 μm wider than both ends of the groove. This alignment requires an accuracy of about 0.1 to 0.2 μm, but the current This is possible by using a reduction projection exposure apparatus (or an electron beam exposure apparatus).

@2 (d): 'I The nitride films 28 and 29 on the diffusion layer are removed by directional plasma etching.

In isotropic plasma etching, low pressure CVD method 11C
The nitride film 29 grown by the plasma CVD method is more easily etched than the nitride film 28 grown by V-grown, and since etching in the horizontal direction precedes etching in the vertical direction, the nitride film 28 is etched. When the nitride film is applied to the oxide film on the surface of the diffusion layer, the nitride film is buried in the groove without any steps on the surface of the diffusion layer, and without any unevenness on the groove that is to become the field region. is completed. Next, the entire oxide film on the diffusion layer is etched, and an oxide film to be a gate oxide film is formed on the diffusion layer. Furthermore, if necessary, ion implantation is performed for dark value voltage control. This ion implantation process is performed except when the impurity concentration on the surface of the semiconductor substrate 210 is already at a value that can provide the expected threshold 1 voltage.

FIG. 2(e): Growing polycrystalline silicon 26 that will become the gate electrode and wiring, and patterning it.
Using the gate polycrystalline silicon as a mask, ion implantation of impurities of a conductivity type opposite to that of the substrate for forming the source/drain 27 is performed using a self-alignment line. Thereafter, a normal manufacturing method is used to fully grow the phosphorus glass layer as an interlayer film, to form contact holes at predetermined positions, and to place metal wiring pipes.

When using the above manufacturing method to separate J, MUS) transistors by other lines, the difference between the designed diffusion layer width (or the diffusion layer width on the mask) and the diffusion layer width on the semiconductor substrate is minimized. If the diffusion layer width is designed to be the same as when using the conventional technology, the reduction in the diffusion layer width due to the selective oxidation will not occur, so the Mus due to the narrow channel effect of the M(JS) transistor Deterioration of transistor characteristics can be reduced. Furthermore, unevenness on the field region and at the boundary between the field region and the diffusion layer region can be made extremely small, making it easy to turn the polycrystalline silicon that will become the gate electrode and wiring.
This has the effect of making it possible to manufacture high-density MUS integrated circuits.

As an embodiment of the present invention, a case in which the above semiconductor device construction method is applied to a manufacturing process of fully complementary MO8 (hereinafter referred to as CMO8) will be described with reference to Fig. wI3.

FIG. 3(a): A P well 311 and an N well 310 are formed in a semiconductor substrate 31 to a predetermined depth. The impurity concentrations in both wells are set to a high enough concentration to prevent channel formation in the field region. This is because when the insulation isolation region is miniaturized, the conductivity type of each well is accurately determined by the P-N switching section at the time of channel strike and impurity ion implantation into the field region. This is to avoid the difficulty of having to ion-implant impurities of the same conductivity type into each well.

After that, approximately 1000A was applied to the surface of the substrate as shown in Fig. 2(a).
After forming the oxide film 33 of about 100 mL, patterning is performed so as to leave the photoresist 34 on the regions that are to become the diffusion layer regions on the n-ah and p-ah sides.

Figure 8g3 (b): As described in the detailed explanation of the present invention, the oxide film 33 in the area to be the field area is etched, and the entire neck area to be the field area is etched by anisotropic plasma etching. After removing the photoresist 34 by etching vertically to a depth of , an oxide film having a thickness of about 500λ is formed in the trench. For the reasons already mentioned, the ion implantation of the channel stopper is excluded here. Thereafter, a nitride film 38 having the same thickness as the depth of the groove is grown by low pressure CVD, and then the nitride film 38 is
After a thin nitride film 39 is entirely grown on 8 by plasma CVD, photoresist patterning is performed to etch the nitride film on the diffusion layer. The procedure in this step has already been described in the detailed description of the present invention.

3rd (9) (C): Utilizing the difference in etching speed between plasma etching of the nitride film by low pressure CVD method and plasma CVD method, the nitride film on the diffusion layer is completely removed by isotropic plasma etching. The filling of the nitride film into the trench is completed by flattening the nitride film 38 in the field region and performing etching so that no step is formed at the boundary between the diffusion layer region and the field region. . After that, the entire oxide film 33 on the diffusion layer is etched.

An oxide film to become a gate oxide film is formed. Next, in order to control the threshold value, impurities of conductivity type opposite to that of each well are ion-implanted into the surface of each well. By this ion implantation, an n-layer 312 is formed near the N-well surface, and a p-layer 313 is formed near the P-well surface. As a result, although each well has a high concentration, the surface layer has a low concentration, so that the mutual conductance of the MOS transistor does not decrease. Furthermore, since the concentration is high below the well, punch-through of the MOS transistor occurs, making it possible to shorten the channel of the i(MOS) transistor.

FIG. 3(d): Polycrystalline silicon 36 to become the gate electrode and wiring is grown and patterned. Next, using the gate polycrystalline silicon as a mask L7, ion implantation for forming the source/drain 37 is performed using an impurity of a conductivity type opposite to that of each well using a self-alignment line.

FIG. 3(e): A phosphorus glass layer 314vr- is grown as an interlayer film by a normal preparation method, contact holes are fully opened at predetermined positions, and metal wiring 315t-, 7m is rubbed. The figure is a sectional view of the final process when the manufacturing method according to the present invention is applied to 0MO8IC.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views in the order of the manufacturing process when the insulation isolation method of MOS transistors according to the prior art is applied, and FIGS. 2(a) to (e) are respectively according to the embodiments of the present invention. M
(J8) Manufacturing process sequence when applying the transistor insulation isolation method (Figure 111 and Figures 3 (a) to (e) are the manufacturing process sequence cross sections when the present invention is applied to obtain a 0MO8IC structure, respectively) In the figure: 11.21.31... Semiconductor substrate, 12...
...CVD nitride film, 13,23.33...Thermal oxide film, 14°24.34...Photoresist, 15
．． 25... Impurity to become a channel stopper, 16,26° 36... Polycrystalline silicon%
17, 27. 37... Source/drain, 28
．． 38...Low pressure CVD nitride film, 29.39...
...Plasma CVD nitride film. 310...N well, 311...P well, 312...n'''' layer, 313...
・p″″ layer, 314... Phosphorus glass layer, 315
・・・・・・Metal wiring. Beam 2 figure 31θ

Claims (1)

[Claims] In the method of manufacturing a field effect semiconductor device using polycrystalline silicon for the gate electrode, in particular the insulation t between transistors is
1i- When performing the above semiconductor substrate mold ii! of the area to be the field area on the semiconductor substrate! a step of etching to a sufficient depth, a step of ion-implanting an impurity of a conductivity type opposite to that of the semiconductor substrate, which is to serve as a channel stopper, and a step of growing a nitride film on the semiconductor substrate in the gap of the groove. , a step of growing a nitride film having a higher etching rate than the nitride film on the nitride film, a step of resist patterning on the above film, and an isotropic plasma etching process. It is characterized by including the step of removing the nitride film on the diffusion layer by utilizing the difference in etching speed of the film, and forming the entire insulation isolation region without a step at the boundary between the field region and the diffusion layer region. A method for manufacturing a semiconductor device.