JPS6143477A - Manufacture of mos transistor - Google Patents
Manufacture of mos transistorInfo
- Publication number
- JPS6143477A JPS6143477A JP16491384A JP16491384A JPS6143477A JP S6143477 A JPS6143477 A JP S6143477A JP 16491384 A JP16491384 A JP 16491384A JP 16491384 A JP16491384 A JP 16491384A JP S6143477 A JPS6143477 A JP S6143477A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- region
- psg
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 8
- 239000011574 phosphorus Substances 0.000 claims abstract description 8
- 239000003870 refractory metal Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 239000004065 semiconductor Substances 0.000 claims 7
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 28
- 238000005468 ion implantation Methods 0.000 abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 24
- 150000002500 ions Chemical class 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- VQHSOMBJVWLPSR-UHFFFAOYSA-N lactitol Chemical compound OCC(O)C(O)C(C(O)CO)OC1OC(CO)C(O)C(O)C1O VQHSOMBJVWLPSR-UHFFFAOYSA-N 0.000 description 1
- 235000010448 lactitol Nutrition 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011435 rock Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＭＯＳ）ランジスタの製造方法に係わり、特に
ソース、ドレイン構造の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a MOS transistor, and particularly to a method of forming a source and drain structure.
近年、ＭＯ８Ｌ８Ｉが高集積化するに伴なってそのゲー
ト寸法がますます微小化し、サブミクロンの領域に入っ
ている。そして、このサブミクロン寸法を有するＭＯＳ
トランジスタは、しきい値電圧がショートチャンネル効
果によりその絶対値の制御が困難となるとともに、ホッ
トキャリアの影響を受けて信頼性の点から不安定となる
問題があった。In recent years, as MO8L8I has become highly integrated, its gate dimensions have become smaller and smaller, entering the submicron range. And MOS with this submicron dimension
Transistors have had problems in that it is difficult to control the absolute value of the threshold voltage due to the short channel effect, and the reliability is unstable due to the influence of hot carriers.
このような問題のうち、ホットキャリアの影響を改善し
たものとしては、第１図に要部断面図で示すようなＬＤ
Ｄ （Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｌｎ ）構
造が例えば、Ｋ、 ５ａｉｔｏ ａｔ ａｌ、” Ａ
ｎｅｗ ５ｈｏｒｔ ｃｈａｎｎｓｌ ＭＯ８ＦＥＴｗ
ｉｔｈ ｌｉｇｈｔｌｙ ｄｏｐｅｄ Ｄｒａｉｎ”
電子通信連合大会、ＰＰ。Among these problems, an LD as shown in the cross-sectional view of the main part in Figure 1 has been developed to improve the influence of hot carriers.
D (Lightly Doped Draln) structure is, for example, K, 5aito at al, "A
new 5hort channel MO8FETw
ith lightly doped Drain”
Electronic Communications Union Conference, PP.
２２０、４月、１９７８．などにより提案されている。220, April, 1978. It has been proposed by et al.
すなわち同図において、Ｐ形シリコンウェハ１上に形成
されたソース領域２およびドレイン領域３には、それぞ
れＮ−ｉ？’ｄ４とＮＪＮ５とが共存し、Ｎ−７５４は
ゲート電極６に接触する領域に形成されている。That is, in the figure, a source region 2 and a drain region 3 formed on a P-type silicon wafer 1 each have N-i? 'd4 and NJN5 coexist, and N-754 is formed in a region in contact with gate electrode 6.
なお、ＴはＰ形シリコンウェハ１上に形成された酸化膜
、８はゲート電極６の側壁に形成されたサイドウオール
５ｉ０２膜である。Note that T is an oxide film formed on the P-type silicon wafer 1, and 8 is a sidewall 5i02 film formed on the side wall of the gate electrode 6.
このように植成されるショートチャンネルＭＯＳトラン
ジスタは、まずＰ形シリコンウェハ１上にゲート’Ｐｌ
！６ｔ−フォトレジスト加工した後、これをマスクとし
て自己３ぼ金的にＮ−／彊４’ｔイオン打込みによって
形成し、次にサイドウオール８１０２膜８をＣＶＤ法に
よるデポジッションとそれに続く異方性エツチング（例
えば反応性イオンエツチングＲＩ Ｅ）法によって形成
した後、これをマスクとして８層５を再度イオン打込み
Ｋよ層形成する。The short channel MOS transistor implanted in this way is first formed with a gate 'Pl' on a P-type silicon wafer 1.
! After processing the 6T-photoresist, this is used as a mask to form a self-containing N-/4't ion implantation process, and then a sidewall 8102 film 8 is deposited using the CVD method, followed by anisotropic deposition. After forming by etching (for example, reactive ion etching RIE), the eight layers 5 are again formed by ion implantation using this as a mask.
しかしながら、イオン打込み磯のイオンビームの打込み
方向は、必らずしもＰ形シリコンウェハ１の平面に対し
て垂直ではない。すなわち、イオン打込み機の形式や種
類が異なった場合、あるいは同一形のイオン打込みイ棧
でも製作年度が異なる場合には、打込み方向はイオン打
込み機によって２度ないし３度またはそれ以上異なるの
が普通である。これはイオン打込みｍ９作工程において
この程度の変動が生じてしまうことに起因している。However, the implantation direction of the ion beam in the ion implantation rock is not necessarily perpendicular to the plane of the P-type silicon wafer 1. In other words, if the model or type of ion implanter is different, or if the same type of ion implanter is manufactured in different years, the implantation direction usually differs by two or three degrees or more depending on the ion implanter. It is. This is due to the fact that this degree of variation occurs during the ion implantation m9 manufacturing process.
したがってミこのようなイオン打込み機が用いられた場
合、例えば最初のＮ−イオン打込み機とそれに続くＮイ
オノ打込み機とが互いに異なった形式のイオン打込み機
である場合または同一形式でも製作年度の異なるイオン
打込み機である場合には、第２図に示すような不都合が
生じてくる。すなわち、まずＮ−イオン打込み機による
打込み方向がＮ方向である場合、ゲート電極６の右側に
おいて、その影によシ、領域Ｓで示されるＮ一層の打込
まれない領域が生ずる。次にＮイオノ打込み機による打
込み方向がＰ方向である場合は、８層５はゲート電極６
の右側においてＮ一層４と重なるのみで領域Ｓの空隙が
生じてしまう。また第３図に示すようにＰ方向の角度が
緩い場合においてはＮ層Ｎ５はＮ−Ｍ４上にオーバーラ
ツプし、ゲート内部 □に食い込むことＫなる
。この結呆、ゲート領域の左側はＮ−領域となっている
が、右側はＮ領域となシ、ＬＤＤ構造から外れるとと忙
なる。つまシ非対称のＬ Ｄ Ｄ ４＋ＩＪ造となって
しまう。Therefore, if such an ion implanter is used, for example, if the first N-ion implanter and the subsequent N-ion implanter are of different types, or even if they are the same type but manufactured in different years. In the case of an ion implanter, problems as shown in FIG. 2 arise. That is, first, when the direction of implantation by the N-ion implanter is the N direction, a region where N is not implanted is created on the right side of the gate electrode 6 due to its shadow, which is indicated by region S. Next, when the implanting direction by the N ion implanter is the P direction, the 8th layer 5 is the gate electrode 6.
On the right side of the layer N, a gap in the region S is created by only overlapping with the layer 4. Further, as shown in FIG. 3, when the angle in the P direction is gentle, the N layer N5 overlaps N-M4 and digs into the inside of the gate. As a result, the left side of the gate region is an N-region, but the right side is an N-region, which becomes busy when it deviates from the LDD structure. It ended up being an LDD 4+IJ construction with asymmetrical tabs.
したがって本発明は［ｊ０述した従来の問題に鑑みてな
されたものであり、その目的とするところはＬ Ｄ Ｄ
ｊｉｉ造に対する２反の打込みプロセスにおいて各々
の打込み角ｊ！◆−が反対符号である場合に発生するＬ
ＤＤも４造の崩れ全防止することのできるＭＯＳ トラ
ンジスタの製造方法を提供することにある。Therefore, the present invention has been made in view of the conventional problems mentioned above, and its purpose is to
In the two-turn driving process for jii structure, each driving angle j! ◆L that occurs when - has the opposite sign
The object of the present invention is to provide a method of manufacturing a MOS transistor that can completely prevent the collapse of DD.
このような目的を達成するために不発明は、ソース領域
のＮ−／黙をサイドウオールＰＳＧからの燐拡散によっ
て形成し、ソース・ドレイン領域のＮ層層をそれに続く
イオン打込みによって形成するものである。In order to achieve such an object, the present invention is to form an N layer in the source region by phosphorus diffusion from the sidewall PSG, and to form an N layer in the source/drain region by subsequent ion implantation. be.
すなわち、ＬＤＤ４７４造のＮ一層形成を、ゲート領域
のサイドウオールＰＳＧ（燐を含むＬＰＣＶＤ ５ｉＯ
ｚ ）膜からの燐の拡散によって行ない、それに続＜
Ｎ層層のみをイオン打込みによって行なう方法である。That is, the formation of a single layer of N in the LDD 474 structure is replaced by the sidewall PSG (LPCVD 5iO containing phosphorus) in the gate region.
z) by diffusion of phosphorus from the membrane, followed by <
This is a method in which only the N layer is implanted by ions.
この場合、イオン打込みはＮ層のみであるから、イオン
打込みの互いの方向差に基づいてＮ一層と１層とのゲー
ト領域端部における重ね合わせ不整合を防止することが
できる。In this case, since ions are implanted only into the N layer, it is possible to prevent overlay mismatch between the N layer and the first layer at the edge of the gate region based on the difference in direction of ion implantation.
次に図面を用いて本発明の実施例を詳細に説明する。 Next, embodiments of the present invention will be described in detail using the drawings.
第４図（１１）〜（ｇ）は本発明によるＭＯＳ）ランジ
スタの製造方法の一例を説明するための要部断面工程図
である。同図において、まず同図（、）に示すようにＰ
形シリコンウェハ１１上に図示しない素子間の分離用絶
縁としてのロコス（ＬＯＣＯ８）酸化［４’を形成した
後、ゲート用８１０２膜１２．リフラクトリ−金属（例
えば、タングステンなど）８Ｍ１３およびＳｉ３Ｎ４膜
１４を通常用いられる手段にょシ順次形成する。この場
合、リフラクトリ−金属薄膜１３１６．２０００〜４０
００ Ａ ｍｅ 、 Ｓ １３Ｎ４膜１４は約５００＾
程度の厚さである。次に同図（ｂ）に示すようにゲート
フォトレジスト処理およびエツチング加工法によ勺５１
３Ｎ４膜１４とリフラクトリ−金属薄ｒ＋免１３ ＜エ
ツチングしゲート領域をパターニングする。引き続き同
図（Ｃ）に示すようにゲート用５ＩＯｚ膜１２ｋＨＦ処
理により除去し、ゲート領域以外のＰ形シリコンウェハ
１１のシリコン面を露出させる。続いて同図（ｄ）に示
すようにＰＳＧ ’ｉ ＬＰＣＶＤ法によって全面にデ
ボジツションし、異方性エツチング（ＲＩＥ）によって
ゲート領域のサイドウオールにＰＳＧ膜１５を形成させ
る。この場合、 ＰＥＧ膜１５の燐濃度は後に形成すべ
きＮ−層の濃度によシ適宜決めることができる。次に同
図（、）に示すようにサイドウオールＰＳＧ１５に覆わ
れていない領域に熱酸化によシ厚さ２００〜５００ Ｘ
程度の８１０ｚ膜１６を形成させて後のＮ＋イオンイン
プラテーション工程の損傷防止膜とする。この場合、サ
イドウオールＰＳＧ膜１５からの拡散によってＰ形シリ
コンウェハ１１の表面には薄いＮ−７ｉＮ７が形成され
る。引き続き同図（ｆ）に示すようにＡ５等のＮ＋不純
物をイオンインプラチージョン法によって打込んだ後、
約１０００℃程度の熱処理を行ってサイドウオールＰＳ
Ｇ膜１５直下のＰ形シリコンウェハ１１には所望のＮ一
層１８がサイドウオールＰＳＧ膜１５からの燐拡散によ
って形成され、Ｎイオノ打込み領域には８層１９がそれ
ぞれ形成される。次にリフラクトリ−金属薄膜１３上の
Ｓｉ３Ｎ４膜１４を燐酸などによシ除去して同図（ｇ）
に示すようなＭＯＳ ）ランジスタが完成される。FIGS. 4(11) to 4(g) are cross-sectional process diagrams of essential parts for explaining an example of a method for manufacturing a MOS transistor according to the present invention. In the figure, first, as shown in the figure (,), P
After forming LOCO8 oxide [4'] as insulation for separating elements (not shown) on the shaped silicon wafer 11, a gate 8102 film 12. A refractory metal (eg, tungsten, etc.) 8M 13 and a Si3N4 film 14 are sequentially formed by commonly used means. In this case, refractory metal thin film 1316.2000~40
00 A me, S 13N4 film 14 is about 500^
It is about the same thickness. Next, as shown in FIG.
3N4 film 14 and refractory metal thin layer 13 are etched to pattern the gate region. Subsequently, as shown in FIG. 5C, the 5IOz film for the gate is removed by 12kHF treatment to expose the silicon surface of the P-type silicon wafer 11 other than the gate region. Subsequently, as shown in FIG. 2D, the entire surface is deposited by the PSG'i LPCVD method, and a PSG film 15 is formed on the sidewalls of the gate region by anisotropic etching (RIE). In this case, the phosphorus concentration of the PEG film 15 can be appropriately determined depending on the concentration of the N- layer to be formed later. Next, as shown in the same figure (,), the area not covered by the sidewall PSG15 is thermally oxidized to a thickness of 200 to 500×.
An 810z film 16 of about 100% is formed to serve as a damage prevention film for the subsequent N+ ion implantation process. In this case, thin N-7iN7 is formed on the surface of the P-type silicon wafer 11 by diffusion from the sidewall PSG film 15. Subsequently, as shown in the same figure (f), after implanting N+ impurities such as A5 by the ion implantation method,
Sidewall PS is heat treated at approximately 1000℃.
A desired N layer 18 is formed on the P type silicon wafer 11 directly under the G film 15 by phosphorus diffusion from the sidewall PSG film 15, and eight layers 19 are formed in each of the N ion implantation regions. Next, the Si3N4 film 14 on the refractory metal thin film 13 is removed using phosphoric acid or the like, as shown in the same figure (g).
A MOS transistor as shown in FIG. 1 is completed.
このような方法によれば、ゲート領域には、デボジツシ
ョンさせたサイドウオールＰＳＧ膜１５の厚さのみの幅
を有するサイドウオールが形成され、これＫよりてＮ一
層１８が形成されるので、第２図。According to this method, a sidewall having a width equal to the thickness of the deposited sidewall PSG film 15 is formed in the gate region, and since the N layer 18 is formed from K, the second figure.
第３図に示すよりなＮ一層４の欠落した間隙は生じない
。また、８層１９はＡ８等のイオン打込みに多少の方向
性があってもＮ一層１８の側面に形成されるので、ＬＤ
Ｄ構造が完成される。A gap where the N layer 4 is missing as shown in FIG. 3 does not occur. In addition, even if the ion implantation of A8 or the like has some directionality, the 8th layer 19 is formed on the side surface of the N layer 18, so the LD
D structure is completed.
以上説明したように本発明によれば、ゲート領域の側壁
にサイドウオールＰＳＧ膜を設け、このＰＳＧからの燐
拡散によってＮ一層を形成し、ソース・ドレイン領域は
それに続くＮイオノ打込みによってＮ層を形成すること
によシ、イオン打込み機の諸条件に全く左右されること
なく、品質、信頼性の高いＬＤＤ＃；４造を有するＭＯ
Ｓトランジスタが生産性良く得られるという極めて優れ
た効果を有する。As explained above, according to the present invention, a sidewall PSG film is provided on the sidewall of the gate region, a single N layer is formed by phosphorus diffusion from this PSG, and an N layer is formed in the source/drain region by subsequent N ion implantation. By forming an MO with a high quality and reliable LDD #4 structure, it is completely unaffected by the conditions of the ion implanter.
This has an extremely excellent effect in that S transistors can be obtained with high productivity.
第１図ないし第３図は従来のＬＤＤ構造を有するＭＯＳ
トランジスタおよびその問題を説明するための要部断面
図、第４図（−）〜（ｇ）は不発ＢＡＫよるＭＯＳトラ
ンジスタの製造方法の一例を説明するための要部断面工
程図である。
１１・・・−Ｐ形シリコンウェハ、１２・＃−・ゲート
用Ｓｉ ０２ ｈａ、１３・・・・す７ラクトリー金属
薄膜、１４・・・・５１ｓＮａ膜、１５・・・Φサイド
ウオールＰＳＧ膜、１６・・・１１Ｓ１０２膜、１Ｔ・
・・・薄いＮ一層、１日・・・・Ｎ一層、１９・・・・
Ｎ層。
第１図
第２図
第３図
第４図
＋７ｉ
（ｂ）
（Ｃ）Figures 1 to 3 show a MOS having a conventional LDD structure.
FIGS. 4(-) to 4(g) are cross-sectional views of main parts for explaining a transistor and its problems, and FIGS. 4(-) to (g) are cross-sectional process views of main parts for explaining an example of a method for manufacturing a MOS transistor using non-exploded BAK. 11...-P type silicon wafer, 12...Si02 ha for gate, 13...7 lacty metal thin film, 14...51sNa film, 15...Φ sidewall PSG film, 16...11S102 membrane, 1T・
...Thin N layer, 1 day...N layer, 19...
N layer. Figure 1 Figure 2 Figure 3 Figure 4 +7i (b) (C)
Claims (1)
膜および表面にリフラクトリー金属膜を有するゲート領
域を形成する工程と、前記ゲート領域を含む半導体ウェ
ハ全面にＰＳＧ層を被覆し異方性エッチングを施すこと
により該ゲート領域側面にＰＳＧ層のサイドウォールＰ
ＳＧ膜を形成する工程と、前記半導体ウェハのゲート領
域を除く領域に熱酸化膜を形成するとともに前記サイド
ウォールＰＳＧ膜の燐を拡散させ半導体ウェハに第１の
導電形と反対の第２導電形を有する半導体層を形成する
工程と、前記熱酸化膜に不純物を打込み半導体ウェハに
第１の導電形と反対の第３導電形を有する半導体層を形
成する工程と、前記半導体ウェハを加熱処理する工程と
を含むことを特徴としたＭＯＳトランジスタの製造方法
。A step of forming an element isolation insulating film and a gate region having a refractory metal film on the surface on a semiconductor wafer having a first conductivity type, and covering the entire surface of the semiconductor wafer including the gate region with a PSG layer and performing anisotropic etching. By applying this, a sidewall P of the PSG layer is formed on the side surface of the gate region.
a step of forming an SG film, and forming a thermal oxide film in a region of the semiconductor wafer other than the gate region, and diffusing phosphorus in the sidewall PSG film to give the semiconductor wafer a second conductivity type opposite to the first conductivity type. forming a semiconductor layer having a third conductivity type opposite to the first conductivity type on the semiconductor wafer by implanting an impurity into the thermal oxide film; and heating the semiconductor wafer. A method for manufacturing a MOS transistor, comprising the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16491384A JPS6143477A (en) | 1984-08-08 | 1984-08-08 | Manufacture of mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16491384A JPS6143477A (en) | 1984-08-08 | 1984-08-08 | Manufacture of mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6143477A true JPS6143477A (en) | 1986-03-03 |
Family
ID=15802235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16491384A Pending JPS6143477A (en) | 1984-08-08 | 1984-08-08 | Manufacture of mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6143477A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63249372A (en) * | 1987-04-03 | 1988-10-17 | Rohm Co Ltd | Manufacture of field effect type transistor |
| JPS6432676A (en) * | 1987-07-29 | 1989-02-02 | Nec Corp | Manufacture of insulated-gate field-effect transistor |
| JPH01134972A (en) * | 1987-10-05 | 1989-05-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JPH0629308A (en) * | 1991-04-10 | 1994-02-04 | Gold Star Electron Co Ltd | Ldd transistor and its manufacture |
| US5434440A (en) * | 1992-05-29 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
| EP0798785A1 (en) * | 1996-03-29 | 1997-10-01 | STMicroelectronics S.r.l. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
| US5698881A (en) * | 1992-05-29 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
-
1984
- 1984-08-08 JP JP16491384A patent/JPS6143477A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5898203A (en) * | 1909-12-11 | 1999-04-27 | Kabushiki Kaisha Toshiba | Semiconductor device having solid phase diffusion sources |
| JPS63249372A (en) * | 1987-04-03 | 1988-10-17 | Rohm Co Ltd | Manufacture of field effect type transistor |
| JPS6432676A (en) * | 1987-07-29 | 1989-02-02 | Nec Corp | Manufacture of insulated-gate field-effect transistor |
| JPH01134972A (en) * | 1987-10-05 | 1989-05-26 | Philips Gloeilampenfab:Nv | Manufacture of semiconductor device |
| JP2547690B2 (en) * | 1991-04-10 | 1996-10-23 | エルジイ・セミコン・カンパニイ・リミテッド | Method for manufacturing LDD transistor |
| JPH0629308A (en) * | 1991-04-10 | 1994-02-04 | Gold Star Electron Co Ltd | Ldd transistor and its manufacture |
| US5434440A (en) * | 1992-05-29 | 1995-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| US5698881A (en) * | 1992-05-29 | 1997-12-16 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
| US5766965A (en) * | 1992-05-29 | 1998-06-16 | Yoshitomi; Takashi | Semiconductor device and method of manufacturing the same |
| US5903027A (en) * | 1992-05-29 | 1999-05-11 | Kabushiki Kaisha Toshiba | MOSFET with solid phase diffusion source |
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
| EP0798785A1 (en) * | 1996-03-29 | 1997-10-01 | STMicroelectronics S.r.l. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
| US5977591A (en) * | 1996-03-29 | 1999-11-02 | Sgs-Thomson Microelectronics S.R.L. | High-voltage-resistant MOS transistor, and corresponding manufacturing process |
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