JPH06204241A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a field effect transistor and manufacturing method thereof capable of decreasing the capacity between the gate and the source and the capacity between the gate and the drain as well as suppressing the fluctuation in the threshold voltage without increasing the channel concentration. CONSTITUTION:A gate electrode forming film comprising a gate film and a gate electrode material is formed on a p type silicon substrate 1 and then these two films are isotropically dry-etched away to pattern these two films so that tapered oxide film extending over the periphery of a gate electrode 3 may be left on the end of a gate oxide film 2a. Next, the p type silicon semiconductor substrate 1 is implanted with n type impurity ions using the gate electrode 3 and the gate oxide film 2a as masks so that the produced impurity layers may be annealed to form source and drain diffused layers 5a, 5b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to high frequency and stabilization of a gate threshold voltage.

[0002]

2. Description of the Related Art FIG. 4 is a sectional view of a peripheral portion of a gate electrode of a conventional N-channel field effect transistor, in which 1 is a P-type silicon semiconductor substrate, 2c is a gate oxide film, 3 is a gate electrode, and 4 is N-type. Arrows indicating the direction of implantation of impurities (for example, phosphorus: P +), 8a and 8b are N-type source / drain diffusion layers formed by implanting the N-type impurities in the P-type silicon semiconductor substrate 1 using the gate electrode 3 as a mask. And 8a
Is a source diffusion layer, and 8b is a drain diffusion layer.

Next, a method of forming a peripheral portion of a gate electrode of a conventional field effect transistor and its features will be described. First, a gate oxide film 2c and then a gate electrode 3 material made of polysilicon or a refractory metal are formed on the entire surface of a P-type semiconductor substrate.

Next, the gate electrode material is processed by anisotropic dry etching to form the gate electrode 3, and the gate oxide film 2c other than immediately below the gate electrode 3 is removed by wet etching.

Next, using the gate electrode 3 as a mask, N-type impurities (for example, phosphorus: P +) are implanted in the implantation direction 4 shown in FIG.
And is annealed at a high temperature of 900 ° C. or higher to form N-type source / drain diffusion layers 8a and 8b. In FIG. 4, the length of the gate electrode 3 is Lg3, the junction depth of the source / drain diffusion layers 8a and 8b is Xj3, and the radius of curvature at the end of the gate electrode is r3. The overlapping lengths of the gate electrode 3 with the source diffusion layer 8a and the drain diffusion layer 8b are ΔLGS3 and ΔLGD3, respectively, and the distance between the source diffusion layer 8a and the drain diffusion layer 8b, that is, the effective channel length is Lgeff3. . Length of gate electrode 3 Lg3
Is expressed as Lg3 = Lgeff3 + ΔLGS3 + ΔLGD3.

The operation of the field effect transistor is performed by applying a positive voltage to the drain diffusion layer 8b and a 0 or negative voltage to the source diffusion layer 8a, and then applying a positive voltage to the gate electrode 3 to directly change the P directly below the gate electrode 3. The surface of the silicon semiconductor substrate 1 is inverted to N-type to form a channel, and the source diffusion layer 8 is formed.
A current flows between a and the drain diffusion layer 8b to show output characteristics.

[0007]

Although the conventional field effect transistor is constructed as described above, in the above-described manufacturing method, the overlapping length ΔLGS3 of the gate electrode 3 and the source diffusion layer 8a and the drain diffusion layer 8b, It is difficult to shorten ΔLGD3, which causes the gate-source capacitance Cgs.
Also, there is a problem that the gate-drain capacitance Cgd becomes large, which hinders high frequency operation of the field effect transistor. Therefore, in order to achieve a high frequency, the overlap lengths ΔLGS3 and ΔLGD3 of the source / drain diffusion layer with the gate electrode are reduced to reduce the gate-source capacitance Cgs and the gate-drain capacitance Cgd. Was needed.

Further, when the gate electrode length Lg3 is shortened, there is a problem that the gate threshold voltage varies due to the short channel effect and stable characteristics cannot be obtained. As a method of suppressing the fluctuation of the gate threshold voltage,
Although there are methods such as increasing the channel concentration, increasing the channel concentration leads to a decrease in the mutual conductance gm and is not preferable for high frequency operation. Therefore, it is necessary to suppress the variation of the gate threshold voltage without disturbing the high frequency operation.

The present invention has been made in order to solve the above problems, and it is possible to reduce the gate-source capacitance Cgs and the gate-drain capacitance Cgd, and without increasing the channel concentration. It is an object of the present invention to obtain a field effect transistor having an element structure capable of suppressing fluctuations in gate threshold voltage and a method for manufacturing the same.

[0010]

A field effect transistor and a method of manufacturing the same according to the present invention include:
Etching is performed under the gate electrode so that the end of the gate oxide film obtained by etching together with the gate electrode remains as a tapered oxide film around the gate electrode, and thereafter, the gate electrode and the gate oxide film are etched. An impurity layer is formed in the semiconductor substrate by ion implantation using as a mask, and the impurity layer is annealed to diffuse to form a source / drain diffusion layer.

Further, in the field effect transistor and the method for manufacturing the same according to the present invention, after the gate electrode is formed by anisotropic etching, an insulating film made of silicon oxide or the like is formed on the substrate so as to cover the gate electrode. After that, the insulating film is anisotropically etched to form a tapered insulating film around the gate electrode portion, and thereafter, ion implantation is performed using the gate electrode and the tapered insulating film as a mask. By this, an impurity layer is formed in the semiconductor substrate, and the impurity layer is annealed to diffuse to form a source / drain diffusion layer.

[0012]

According to the present invention, the gate electrode is formed so that the end of the gate oxide film remains as a tapered oxide film around the gate electrode, and in this state, ion implantation is performed using the gate electrode and the gate oxide film as a mask. By source
Since the drain diffusion layer is formed, the concentration distribution along the taper of the tapered oxide film is smaller in the substrate immediately below the tapered oxide film around the gate electrode than in the other regions. Is formed, and the interface shape of the gate-side end of the source / drain diffusion region formed by annealing this is also a shape close to the taper of the tapered oxide film, and the amount of penetration into the area directly below the gate electrode is also Get smaller. Therefore, the amount of penetration of the source / drain diffusion region directly below the gate electrode is reduced, so that the gate-source capacitance Cgs and the gate-drain capacitance Cgd are reduced, and the cutoff frequency can be improved. Since the interface shape at the gate side end of the drain diffusion region has a shape close to the taper of the tapered oxide film,
The radius of curvature of this interface shape can be increased without deeply forming the source / drain diffusion regions, strain on the equipotential surface immediately below the gate electrode can be relaxed, and fluctuations in the gate threshold current can be suppressed.

Further, in the present invention, after the gate electrode is formed by anisotropic etching, an insulating film is formed so as to cover the gate electrode, and the insulating film is etched to form a taper around the gate electrode. Since the insulating film is formed as described above, when the source / drain diffusion region is formed in the same manner as described above, the interface shape of the gate-side end portion becomes a shape close to the taper of the tapered insulating film, and the cutoff frequency is It can be improved and the fluctuation of the gate threshold current can be suppressed. Further, since the gate electrode is formed by anisotropic etching before forming the tapered insulating film, the controllability of the processing size of the gate electrode is excellent and the operating characteristics can be further improved.

[0014]

EXAMPLES Example 1. 1 is a sectional view showing the structure of an N-channel field effect transistor according to a first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 denote the same or corresponding portions, 2a denotes a gate oxide film, 5a, 5b
Is a source diffusion layer and a drain diffusion layer formed by implanting N-type impurities into the P-type silicon semiconductor substrate 1. Also,
In the figure, the length of the gate electrode is Lg1, the lengths of the overlapping portions of the gate electrode 3 with the source diffusion layer 5a and the drain diffusion layer 5b are ΔLGS1 and ΔLGD1, respectively, and the distance between the source diffusion layer 5a and the drain diffusion layer 5b, That is, the effective channel length is Lgeff1, the depth of the source / drain diffusion layers 5a and 5b is Xj1, and the radius of curvature of the gate-side vicinity thereof is r1. The gate electrode length Lg3 is expressed as Lg3 = Lgeff3 + ΔLGS3 + ΔLGD3.

Next, a method of manufacturing the N-channel field effect transistor and its characteristics will be described. First, in FIG. 1, a thermal oxide film is formed as a gate oxide film 2a on the entire surface of the semiconductor substrate 1 by a wet method or a dry method, and then a gate electrode material made of polysilicon or a refractory metal is formed on the gate oxide film 2a. 3 is formed on the entire surface.

After that, a pattern is formed on the gate electrode material 3 with a photoresist and isotropic dry etching using a gas such as CF4 or SF6, that is, plasma etching by a parallel plate electrode or a downflow method is performed. The gate electrode material 3 and the gate oxide film 2a are etched. At this time, the etching conditions are set so that the gate electrode 3 has a predetermined size, but since it is isotropic etching, the end portion of the gate oxide film 2a remains in a tapered shape around the gate electrode 3. . That is, the selection ratio between the gate electrode material 3 and the gate oxide film 2a is 1 or more, and when the gate electrode material is over-etched,
The taper shape, particularly the taper angle is determined by the magnitude of the selection ratio between the gate electrode material and the gate oxide film. When the selection ratio is increased, a taper shape with a wide skirt can be obtained. The taper shape of the oxide film can be formed by giving the taper of the oxide film a salient name for the width of the skirt of the resist pattern when the gate electrode is processed.

Next, N-type impurities (for example, phosphorus: P +)
Is implanted into the P-type silicon semiconductor substrate 1 using the gate electrode 3 and the gate oxide film 2a as an implantation mask.
Annealing is performed at a high temperature of 0 ° C. or higher to form the source / drain diffusion layers 5a and 5b. At this time, in the substrate 1 immediately below the tapered oxide film at the end of the gate oxide film 2a,
Impurities are implanted at a concentration lower than that of the other regions, and the concentration distribution becomes a concentration distribution corresponding to the tapered shape of the tapered oxide film. Therefore, the interface shape of the gate side end of the source / drain diffusion region formed by annealing this is
The tapered oxide film has a shape close to the tapered shape, and the amount of penetration into the area directly under the gate electrode 3, that is, ΔLGS1, ΔL
GD1 also becomes smaller.

In such an N-channel field effect transistor of this embodiment, the source / drain diffusion layers 5a, 5 are formed.
Insertion amount ΔL of the N-type impurity implantation under the gate electrode of b
GS1 and ΔLGD1 are smaller than before (that is, ΔLG
S1 <LGS3, ΔLGD1 <ΔLGD3), the gate-source capacitance Cgs, and the gate-drain capacitance Cgd can also be significantly reduced compared to the conventional one, and the cutoff frequency fT is fT = gm / (2π · (Cgs + Cgd) ), The cutoff frequency fT can be improved, and excellent high frequency operation can be performed.

Further, the source / drain diffusion regions 5a, 5
Since the interface shape of the gate side end of b is close to the taper of the tapered oxide film, the radius of curvature r1 of the interface of the gate side end is not formed deeply in the source / drain diffusion regions 5a and 5b. Grows larger. That is, the source
When the junction depth Xj1 of the drain diffusion layers 5a and 5b is the same as the junction depth Xj3 of the source / drain diffusion layers 8a and 8b of the conventional N-channel field effect transistor shown in FIG. The radius of curvature r1 can be made larger than that of the conventional one (r3 of the radius of curvature in FIG. 4). Therefore,
When the gate electrode length Lg1 is shortened to, for example, 1 μm or less, a positive potential is applied to the drain, 0 or a negative voltage is applied to the source, and a positive potential is gradually applied to the gate. Is the source / drain diffusion layer 5
Since the radius of curvature r1 of the gate side ends of a and 5b is large, the distortion is small, and as a result, the fluctuation of the threshold voltage due to the short channel effect is suppressed and excellent high frequency operation can be performed. It will be possible.

Example 2. 2 is a sectional view showing the structure of an N-channel field effect transistor according to the second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 designate the same or corresponding parts. 2b is a date oxide film. In this N-channel type field effect transistor, the tapered oxide film portion formed at the end of the gate oxide film 2a of the N-channel type field effect transistor of the first embodiment is formed into the source / drain diffusion layers 5a and 5b. After formation, it is removed by a wet etching method or the like.

In such an N-channel field effect transistor of this embodiment, since the tapered oxide film at the end of the gate oxide film 2a is removed, the gate oxide film 2b is tapered when a voltage is applied to the gate. -Source capacitance Cgs and gate-drain capacitance Cgd
Can be suppressed, and the high frequency operation characteristics can be further improved as compared with the N-channel field effect transistor of the first embodiment.

Example 3. FIG. 3 is a cross-sectional view showing the steps of manufacturing an N-channel field effect transistor according to the third embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same or corresponding portions, and 2c denotes a gate. An oxide film, 6 is an insulating film made of silicon oxide or the like formed by chemical vapor deposition or coating after processing the gate electrode 3,
Reference numeral 7 is a tapered insulating film. In the figure, the length of the gate electrode 3 is Lg2, the depth of the source / drain diffusion layers 5a and 5b is Xj2, and the radius of curvature of the end portion on the side of the gate electrode 3 is r2. The overlapping lengths of the layers 5bj are ΔLGS2 and ΔLGD2, respectively, and the distance between the source diffusion layer 5a and the drain diffusion layer 5b, that is, the effective channel length is Lgeff2. Gate electrode 3 length L
g2 is expressed as Lg2 = Lgeff2 + ΔLGS2 + ΔLGD2.

Next, a method of manufacturing the N-channel field effect transistor will be described. First, a gate oxide film 2c is formed on the entire surface of the P-type semiconductor substrate 1, and a gate electrode material made of polysilicon or a refractory metal is formed thereon. Then, a pattern made of photoresist is formed on the film made of the gate electrode material, and the film made of the gate electrode material is etched by an anisotropic dry etching method using this pattern as a mask to form the gate electrode 3 and then wet. After removing the gate oxide film 2c except under the gate electrode 3 by the etching method, the insulating film 6 made of silicon oxide or the like is formed on the entire surface of the P-type semiconductor substrate 1 by the chemical vapor deposition method or the coating method. The state shown in 3 (a) is obtained. Then, after this, as shown in FIG.
By anisotropic dry etching method using gas such as 3
When the insulating film 6 is etched by a predetermined amount, a portion where the layer thickness is formed thick, that is, the insulating film around the gate electrode is left, and a tapered insulating film 7 is formed around the gate electrode 3. . Next, the gate electrode 3 and the tapered insulating film 7
And are used as implantation masks to form N on the P-type silicon semiconductor substrate 1.
Form impurity implantation (for example, phosphorus: P + implantation)
The source and drain diffusion layers 5a and 5b are formed by annealing at a high temperature of ℃ or more.

In the manufacturing process of the N-channel field effect transistor of this embodiment, the tapered insulating film 7 is formed around the gate oxide film 3, and the source,
Since the drain diffusion layers 5a and 5b are formed,
Similar to the first embodiment, the source / drain diffusion region 5 is formed.
The interface shape of the gate-side end portions of a and 5b becomes a shape close to the tapered shape of the tapered insulating film 7, and the amount of penetration into the area directly below the gate electrode 3, that is, ΔLGS1 and ΔLGD1 also becomes small. Therefore, similarly to the first embodiment, the gate-source capacitance Cgs and the gate-drain capacitance Cgd are reduced,
The cutoff frequency can be improved, and the radius of curvature r2 of the end portion on the gate electrode 3 side increases along the taper shape of the tapered insulating film 7 without forming the source / drain diffusion regions 5a and 5b deep. Therefore, the fluctuation of the threshold voltage due to the short channel effect can be suppressed. Further, in the first embodiment, the end portion of the gate oxide film 2a is formed into a tapered shape when the gate electrode 3 is formed. Therefore, the gate electrode 3 is formed by the isotropic dry etching method.
However, there is a drawback that the taper shape varies due to variations in etching conditions and the like, and element characteristics tend to vary. However, in the manufacturing process of this example, the gate electrode 3 is anisotropically dry-etched. Since it is formed by the method, the controllability of the processing dimension is good, the gate electrode can be miniaturized with high accuracy, and the device characteristics can be further improved. In the above manufacturing process, the tapered insulating film 7 may be removed after the source / drain diffusion layers are formed in the same manner as in the second embodiment. Similarly, the gate-source capacitance Cgs and the gate-drain capacitance Cgd can be further reduced.

In each of the first to third embodiments, the impurity is implanted from the direction perpendicular to the substrate plane when forming the source and drain diffusion layers. It suffices that the tapered shape of the tapered insulating film provided in the peripheral portion of the electrode can be reflected on the impurity implantation concentration and concentration distribution, and the impurity implantation can also be performed by tilt angle implantation or rotational implantation having a tilt angle. .

Further, although the N-channel type field effect transistor has been described in the above first to third embodiments, it is needless to say that the present invention can be applied to the P channel type field effect transistor.

[0027]

As described above, according to the present invention, when the gate electrode is formed, etching is performed so that the tapered oxide film is left at the end of the gate oxide film below the gate electrode. Further, since the source / drain diffusion layer is formed by annealing the impurity layer formed in the semiconductor substrate by ion implantation using the gate oxide film as a mask, the interface of the source / drain diffusion region on the gate side end portion is formed. The shape is the shape inheriting the tapered shape of the end of the gate oxide film, and the gate-source capacitance Cgs,
The gate-drain capacitance Cgd is reduced, and the equipotential surface directly under the gate electrode is relaxed as compared with the conventional one, resulting in an improved cutoff frequency and a small variation in the gate threshold current. Further, there is an effect that a field effect transistor excellent in high frequency operation can be obtained.

Further, according to the present invention, after the gate electrode is formed to a predetermined width by anisotropic etching, a tapered insulating film is formed around the gate electrode portion, and the gate electrode and the tapered insulating film are insulated. Since the source / drain diffusion layer is formed by annealing the impurity layer having the impurity layer formed in the semiconductor substrate by ion implantation using the film as a mask, the same effect as described above can be obtained, and the gate can be obtained. Since the electrodes can be miniaturized with high accuracy, there is an effect that a field effect transistor with further improved operating characteristics can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view for each step showing the manufacturing process of the field effect transistor according to the third embodiment of the invention.

FIG. 4 is a cross-sectional view showing the structure of a conventional field effect transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon semiconductor substrate 2a, 2b, 2c Gate oxide film 3 Gate electrode 4 Arrow which shows the injection direction of N-type impurity 5a Source diffusion layer 5b Drain diffusion layer 6 Insulating film made of silicon oxide 7 Tapered insulating film 8a Source diffusion layer 8b Drain diffusion layer

Claims (8)

[Claims] 1. A method of manufacturing a field effect transistor, comprising forming a gate electrode and a gate oxide film under the gate electrode on a semiconductor substrate by etching, comprising: forming a gate oxide film on a semiconductor substrate; A step of forming a gate electrode forming film made of a gate electrode material on the film, and a step of etching the gate oxide film and the gate electrode forming film by an isotropic dry etching method to form a gate electrode having a predetermined width And a step of forming an impurity layer in the semiconductor substrate by ion implantation using the gate electrode and the gate oxide film as a mask and diffusing the impurity layer by annealing to form a source / drain diffusion layer. Of manufacturing a field effect transistor having the same. 2. The method of manufacturing a field effect transistor according to claim 1, wherein after forming the source / drain diffusion layer, a tapered end portion of the gate oxide film is removed by etching, and a width thereof is formed. To have the same width as the gate electrode. 3. A field effect transistor formed by etching a gate electrode and a gate oxide film below the gate electrode on a semiconductor substrate, wherein the gate oxide film has an end portion around the gate electrode. The electric field is characterized in that the source / drain diffusion layers are etched so as to spread in a tapered shape and are formed by annealing the above-mentioned gate electrode and the impurity layer formed by ion implantation using the gate oxide film as a mask. Effect transistor. 4. The field effect transistor according to claim 3, wherein the tapered end portion of the gate oxide film is removed after the source / drain diffusion layer is formed. Transistor. 5. A method for manufacturing a field effect transistor, which comprises forming a gate electrode and a gate oxide film below the gate electrode on a semiconductor substrate by etching, wherein the gate oxide film is formed on the semiconductor substrate. A step of forming a gate electrode forming film made of a gate electrode material on the upper surface, and patterning the gate electrode forming film by anisotropic etching to form a gate electrode having a predetermined width, and then immediately below the gate electrode. A step of removing a gate oxide film other than the above by etching, a step of forming an insulating film on the entire surface of the semiconductor substrate by a chemical vapor deposition method or a coating method so as to cover the gate electrode, the gate electrode and the gate A step of anisotropically etching the insulating film so that a tapered insulating film remains around the oxide film; Forming a source / drain diffusion layer by forming an impurity layer in the semiconductor substrate by ion implantation using the taper-shaped insulating film obtained in the above step as a mask, and diffusing the impurity layer by annealing. And a method for manufacturing a field effect transistor. 6. The method of manufacturing a field effect transistor according to claim 5, wherein the tapered insulating film is removed by etching after the formation of the source / drain diffusion layer. Method. 7. A field effect transistor in which a gate electrode is formed on a semiconductor substrate by anisotropic etching, and a gate oxide film under the gate electrode has its end removed so as to have the same width as the gate electrode. An insulating film formed into a tapered shape is formed around the gate electrode and the gate oxide film, and a source / drain diffusion layer is formed by ion implantation using the gate electrode and the insulating film as a mask. A field-effect transistor, characterized in that it is formed by annealing a layer. 8. The field effect transistor according to claim 7, wherein the tapered insulating film is removed after forming the source / drain diffusion layers.