JPS61220372A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form source-drain regions by doping an impurity by shaping a gate electrode through a gate insulating film, forming a semiconductor film to the side section of te gate electrode on source-drain forming prearranged regions and using the gate electrode as a mask. CONSTITUTION:A field insulating film 2 is shaped to a p<-> type Si substrate 1, and a gate electrode 4 by a polycrystalline silicon film is formed through a gate oxide film 3. An SiO2 film 7 is deposited on the whole surface, the SiO2 film 7 is left only on the side wall of the gate electrode 4 through etching, an Si3N4 film 8 is deposited on the whole surface, and the film 8 is etched to leave the Si3N4 film 8 only on the outside of the SiO2 film 7. An SiO2 film 9 is shaped, the Si3N4 film 8 is removed selectively, and openings are bored where adjacent to the gate electrode 4 in sourcedrain forming prearranged regions. Si films 10 are grown selectively on the substrates exposed to the opening sections, the SiO2 film 9 is removed, and n<+> type layers 11, 12 are formed in source-drain regions through the implantation of As ions and heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method for manufacturing an insulated gate type (MOS type) semiconductor device.

[Technical background of the invention and its problems]

In MO3 integrated circuits, as elements become smaller, it is becoming difficult to form sources and drains using diffusion layers having shallow junctions based on so-called proportional shrinkage agents. Therefore, the short channel effect, in which the threshold value decreases as the channel length decreases, has become a problem. Furthermore, when devices are miniaturized, hot electrons are generated due to impact ionization in a high electric field region near the drain, which adversely affects device characteristics. In order to alleviate such high electric fields, so-called LDD (Liah
However, it is possible to scale down and use this LDD structure in a microscopic device.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing an MO8 type semiconductor device that solves the above-described problems.

[Summary of the invention]

In the present invention, after forming a gate electrode on the semiconductor surface of a substrate via a gate insulating film, for example, selective CV
A semiconductor film is formed using D technology, and then impurities are doped using the gate electrode as a mask to form the source,
It is characterized by forming a drain region.

(Effects of the Invention) According to the present invention, the semiconductor film is selectively formed on the side of the gate electrode on the region where the source and drain are to be formed to form the source and drain regions. In the portion where the bonding surface of the gate electrode is adjacent to the gate electrode, it is possible to control the bonding surface so that it is located at approximately the same position as the interface between the gate insulating film and the semiconductor substrate, or located above it. As a result, an effectively extremely shallow source/drain junction depth can be obtained in the vicinity of the gate electrode.

Therefore, according to the present invention, it is possible to alleviate the short channel effect caused by a decrease in channel length.

In addition, as a result of selectively forming a semiconductor film on the side portions of the gate electrode to form the source and drain, the junction surface of the source and drain can be made to have the same shape as the LDD structure.
Similar to the LDD structure, it is possible to effectively suppress the hot electron effect caused by impact ionization near the drain of a microscopic element.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 7 are cross-sectional views of the manufacturing process of an MoS transistor according to an embodiment.

First, a field insulation wA2 is formed on a p-type 3i substrate 1 by selective oxidation or the like, and a gate electrode 4 made of a polycrystalline silicon film is formed in an element region via a gate oxide film 3 according to a normal process. In the regions where the source and drain are to be formed,
Using the gate electrode 4 as a mask, ultra-shallow, low-concentration n-type layers 5 and 6 are formed by ion implantation such as AS (Fig. 1).
. The field insulation vA2 may be formed by the burying method.3 Next, the SiO2 film 7 is deposited on the entire surface by the CVD method, and this is etched by reactive ion etching (RIE) to form the SiO2 film 7 only on the side walls of the gate electrode 4. Furthermore, a Si3N+ film 8 is deposited on the entire surface by CVD, and this is etched by RIE, leaving the 5iiN+ film 8 only on the outside of the SiO2 film 7 (FIG. 2).

Thereafter, a SiO2 film 9 is formed by thermal oxidation on the surface of the regions where the gate electrode 4 and the source and drain are to be formed (FIG. 3). Then, the Si3N4 film 8 is coated with phosphoric acid or CF3 and 02
This is selectively removed by a CDE method using a gas containing N2 and N2, and an opening is provided at a position adjacent to the gate electrode 4 in the region where the source and drain are to be formed (FIG. 4).

Next, a 3i film 10 is selectively grown on the substrate exposed in the opening by selective epitaxial method (FIG. 5). Then, using ammonium fluoride solution, the gate electrode 4 and the source,
S f 02 g on the region where the drain is to be formed! 9 is removed, and n4 type layers 11 and 12 are formed in the source and drain regions by ion implantation of As and heat treatment at 900° C. for about 60 minutes (FIG. 6).

8102 film 13 is deposited on the entire surface by CVD using the normal process.
A contact hole is opened in this deposited by
Source and drain electrodes 14 and 15 are formed using the J2 film (FIG. 7).

According to this embodiment, 81 is located adjacent to the gate electrode.
Since the source and drain regions are formed by selectively growing the film and performing ion implantation, it is possible to form extremely shallow source and drain junctions adjacent to the gate electrodes, as shown in Figures 6 and 7. can be formed. That is, in the portion adjacent to the gate electrode, the junction surface of the source and drain regions is located at approximately the same position as the interface between the gate insulating film and the substrate, or in some cases above this interface.
It can be formed with good controllability. Therefore, a fine MO3FE with a channel length of about 1 μm or submicron
Even if T, a decrease in the threshold voltage due to the short channel effect can be suppressed.

Furthermore, by controlling the thickness of the 3i film by selective epitaxial method, the shape of the junction surface of the source and drain regions can be arbitrarily controlled, and the shape of the electric field distribution in the channel region can be made preferable. As a result, L.D.
Similar to the D structure, it is possible to reduce the high electric field near the drain region and suppress the hot electron effect in the fine MO3FET.

Furthermore, process control is easier than in the case where source and drain regions with shallow junction surfaces are formed by extremely shallow ion implantation, and therefore highly reliable and fine MO5FETs can be manufactured with a high yield.

Note that the present invention is not limited to the above-mentioned embodiments, but can also be applied to, for example, SO8 semiconductor devices. Also selectively 3i
As a method of forming the film 10, it is also possible to form a Si film on the entire surface of the substrate and to leave only selected portions by etching it. The pond water invention can be implemented with various modifications.

[Brief explanation of drawings]

1 to 7 are MOSFETs according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining the manufacturing process of ET. 1...p-type Si substrate, 2...field insulating film,
3... Gate insulating film, 4... Gate electrode, 5, 6...
... n- type layer, 7... SiO2 film, 8-8-3i+ film, 9... SiO2 film, 10... Si film (selective growth film), 11.12... O4 type layer, 13...SiO2 film, 14°15...source, drain electrode. Applicant's agent Patent attorney Takehiko Suzue Figure 5 Figure 6 Figure 7

Claims (3)

[Claims] (1) a step of forming a gate electrode on the semiconductor surface of the substrate via a gate insulating film; a step of partially forming a semiconductor film on the region where the source and drain are to be formed on the side of the gate electrode; 1. A method of manufacturing a semiconductor device, comprising the step of doping impurities using a gate electrode as a mask to form source and drain regions. (2) The method for manufacturing a semiconductor device according to claim 1, in which the semiconductor film is formed by selective CVD. (3) The step of selectively growing a semiconductor film on the side of the gate electrode on the region where the source and drain are to be formed is the step of selectively forming a SiO_2 film on the sidewalls of the gate electrode in the region where the source and drain are to be formed. a step of selectively forming a Si_3N_4 film on the sidewalls of the gate electrode on which the SiO_2 film is formed; a step of forming the SiO_2 film on the remaining portions of the regions where the source and drain are to be formed;
A process of selectively etching the N_4 film and removing the Si_4 film.
2. The method of manufacturing a semiconductor device according to claim 1, comprising the step of selectively epitaxially growing a semiconductor film in the opening from which the 3N_4 film has been removed.