JPH01304783A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To maintain the performance of a MOSFET by a method wherein a process of forming a semiconductor layer of the opposite conductive type to a substrate on the substrate having an included surface and a process levelling the semiconductor layer are inclined, the semiconductor layer is made the first and second electrodes and the substrate in the region put between the inclined surfaces is made a channel region. CONSTITUTION:A two-layer consisting of an oxide film 12 and a nitride film 12' is made to grow on a semiconductor substrate 11, the substrate 11 is etched with a hydrazine solution and a trapezoidal part 11b having an inclined surface 11a is made under an SiO2 film 12. Next, a semiconductor whose allover is doped to be of the opposite conductive type to the substrate 11 is formed by vapor phase epitaxy for making a semiconductor layer 13 and polycrystalline silicon 13' is removed by levelling using a resist or the like so that the semiconductor layer 13 to be first and second electrodes of a MOSFET to be formed remains. Further, a gate insulating film 15 and a gate electrode 16 are made to grow on the SiO2 film on a channel region to finish the MOSFET, where the substrate part under the gate insulating film 15 is to be the channel. Thereby, characteristic deterioration can be prevented.

Description

[Detailed Description of the Invention] [Summary of the Invention] This invention relates to a method of manufacturing semiconductor devices, particularly a method of manufacturing fine transistors used in high-speed, high-density circuits (ultra-LSI) using semiconductors, by compensating for the drawbacks of the LDD structure and manufacturing MOSFETs. The purpose of this study is to propose a method for creating a new structure to maintain the performance of a semiconductor substrate. a step of growing a semiconductor layer of a conductivity type opposite to that of the substrate on the substrate, and a step of flattening the semiconductor layer, using the semiconductor layer as a first and second electrode, and sandwiching the semiconductor layer between inclined surfaces. The present invention includes a method for manufacturing a semiconductor device using a substrate in a region as a channel.

[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a fine transistor used in a high-speed, high-density semiconductor circuit (ultra LSI).

[Prior Art] In recent MOSFETs (metal oxide semiconductor field effect transistors), the gate length, which determines performance, has become less than 1 μm.

As dimensions have become finer, the depth of the bond has come to determine performance. In other words, deep joints cause punch-through,
Parasitic resistance increases in shallow junctions.

In addition, if the junction is shallow, the curvature of the concentration profile near the gate edge becomes small, generating a large number of hot carriers and making it easy to deteriorate. There is a need for new structural joints that solve all of these problems. For this reason, LDD (Light
(Tly Doped Drain) structure has been proposed, but since it is simply a combination of a shallow junction and a deep junction, the curvature of the concentration profile at the gate edge and the parasitic resistance have not been solved, so it is necessary to solve the above problems. There is.

Punch-through described above occurs when a voltage is applied between the source and drain, the depletion layer expands and sticks together, and current flows between the source and drain, making it impossible to control the current even if the applied voltage is changed. Punch-through is a phenomenon that depends on the source and drain concentrations, substrate concentration, gate length, and junction depth.

Therefore, it is possible to make the junction depth shallower, but the parasitic resistance R when current flows from the source to the drain is determined by the following equation, and as the junction depth becomes smaller, R increases.

However, L is the gate length, W is the gate width, Xj is the junction depth, and ρ is the sheet resistance.

Electrons flowing from the source to the drain near the gate edge are accelerated, and when these electrons collide with the junction surface, they are ionized and create electrons and holes. Electrons or holes (hot carriers) created by this impact ionization enter the gate insulating film or the interface between the insulating film and the semiconductor, causing device deterioration. The generation of hot carriers is
It is influenced by junction curvature as well as gate length, voltage, and impurity concentration.

The process of forming an LDD structure MO3FET will now be described with reference to FIG.

Refer to FIG. 2(a): On a semiconductor substrate 1, a gate insulating material thin film 2a and a gate 1/electrode material thin film 3a are grown in order.

Referring to FIG. 2(b), the gate structure of the gate insulating film 2 and gate electrode 3 (2, 3
) to form.

See Figure 2(C): Ion implantation using the gate structure (2, 3) as a mask,
A shallow ion implantation region 5 (junction depth Xjl) is formed.

See Figure 2(d): The gate electrode 3 is covered with an insulating film 6 that will become side walls in a later process.

See FIG. 2(e): The insulating film 6 is etched, for example, by reactive ion etching, leaving sidewall portions 6a on both sides of the gate electrode 3.

Refer to FIG. 2(f): Deeper than the ion implantation region 5 formed in the previous step using the gate structure (6a 3-6a) including the sidewall portion 6a as a mask (junction depth x; Z > x J,) Ion implantation is performed in region 7.

See FIG. 2(g): The ion implanted regions 5.7 are activated to become source and drain regions (8, 9), and a cover insulating film 10 is applied.

In the LDD structure formed by the above steps, as long as ions are implanted using the rectangular gate as a mask, there will always be a junction plane perpendicular to the channel plane due to the impurity wrapping under the gate electrode. Since the junction depth Xj cannot be made zero, a shallower diffusion technique is always required to create a finer LDD structure. Moreover,
In order to make the junction shallower with current ion implantation technology, the surface impurity concentration after ion implantation must be lowered.
This causes performance deterioration of SFET.

[Problem to be solved by the invention]

As mentioned above, there are two ways to form the short channel MO5: to make the junction extremely shallow or to use an LDD type.

However, it is technically difficult to form an extremely shallow junction with a sufficiently large carrier concentration using the conventional ion implantation method. Therefore, if an LDD structure is used, it is necessary to make the junction shallower in a stepwise manner from a place far from the gate electrode toward both ends of the lower surface of the gate electrode, which increases the number of steps. In addition, since ion implantation is performed using a rectangular gate structure perpendicular to a horizontal substrate, there is always a junction plane perpendicular to the substrate, and in that case, between the vertical junction planes that are parallel to each other, the vector of the electric field E and the vector of the current I are in the same direction, and the generation of hot carriers is maximized. Therefore, it is necessary to prevent the electric field vector from being parallel to the current vector to suppress the generation of hot carriers. Thus, as channel lengths decrease, increasingly shallow junction formation techniques are required.

Therefore, the present invention compensates for the drawbacks of the LDD type and
The purpose is to propose a method for creating a new structure to maintain the performance of

[Means for Solving the Problem] The above problem consists of a step of providing a mask region on a semiconductor substrate and anisotropically etching the substrate, and a step of etching the substrate on the substrate having an inclined surface created by the anisotropic etching. a step of growing a semiconductor layer of a conductivity type opposite to that of the semiconductor layer, and a step of planarizing the semiconductor layer. The problem is solved by a method of manufacturing a semiconductor device.

(Function) In the method of the present invention, a Si0g mask is provided on the surface of the Si substrate with the plane orientation (100), and an etching solution of (1
The (111) and (110) planes are etched slowly.

(However, the temperature is 100°C.) The groove etched at this time is formed by inclined side walls having an angle of 55°C from both ends of the 5i02 mask and a bottom face in the (100) plane orientation. This 1-degree slope is used as it is as the slope of the source/drain junction region, and the following effects can be obtained by this method.

■ Do not create a joint surface perpendicular to the channel part.

■ Make the junction depth 0 near the gate electrode.

■ Compared to forming a stepped joint, it can be formed in one step.

■ Increase the impurity concentration near the gate electrode compared to when forming a stepped junction.

(Example〕 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

FIG. 1 is a diagram showing the steps of carrying out the method of the present invention.

Refer to FIG. 1(a): An oxide film (SiO □
A two-layer film consisting of a film) 12 and a nitride film (SiN film) 12' is grown and patterned. SiO□ film 12 film bottom 2.

The number of participants is approximately 200, and the thickness of the SiN film 12' is approximately 500.

See Figure 1(b): For example, hydrazine (NZI+4) 80%, water (H2O
) 20%, 100″C solution to the substrate 11 to a depth of 0.2
After μm etching, the SiO□ film 12 film bottom 2 inclined surface 11
Make b on the trapezoid part with a.

Refer to FIG. 1(C): A semiconductor layer 13 is formed by epitaxially growing a semiconductor (for example, silicon) doped with a conductivity type opposite to that of the substrate 11 to a thickness of 0.5 μm. Polycrystalline silicon 13' grows in the area surrounded by the broken line in the figure, but single-crystal silicon grows in the area in contact with the substrate 11, and since this single-crystal silicon is doped to have the opposite conductivity type as the substrate, it is difficult to There is an advantage that an impurity diffusion step (for example, ion implantation) for forming sources and drains is omitted in the process.

Referring to FIG. 1(d), a conventional planarization process is performed using a resist or the like, and the planarization is stopped when the SiN film 12' is exposed.

Note that this planarization removes the polycrystalline silicon 13', leaving the semiconductor layer 13 that will become the first and second electrodes of the MOSFET to be formed.

See FIG. 1(e): An insulating oxide film 1 of about 0.1 μm is formed on the semiconductor layer 13.
Oxidation is performed so that 4 grows. At this time, the SiN film 12' serves as an oxidation-resistant mask.

Refer to Figure 1): Remove the SiN film 12' from the SiO□ film on the channel region, grow a new gate insulating film 15 to a thickness of, for example, 500 nm, and grow polysilicon that will become the gate electrode 16. and pattern it to a predetermined size.

Thereafter, a MOSFET in which the semiconductor layer 13 is used as the first and second electrodes and the substrate portion under the gate insulating film 15 is used as a channel is completed using a normal process, but the scope of application of the present invention is limited to that case. It is not something that can be done.

(Effects of the Invention) As described above, according to the present invention, the MOSFET source
As the drain electrode, a junction that is shallow near the gate and becomes deeper as it moves away from the gate can be easily obtained, and even if a short channel FET is fabricated, short channel effects will not appear and characteristic deterioration can be prevented. Furthermore, since this inclined junction region does not have a plane perpendicular to the straight line from the source to the drain, the slope of the electric field between the source and drain does not become parallel to the direction of the current, which has the effect of making it difficult for hot carriers to be generated.

[Brief explanation of the drawing]

Figures 1 (a) to (f) are cross-sectional views of embodiments of the present invention, and Figure 2 (
a) to (2) are cross-sectional views of the LDD structure formation process. In the figure, 11 is a semiconductor substrate, 11a is an inclined surface, 11b is a trapezoidal part, 12 is a SiO□ film, 12' is a SiN film, and 13 is a semiconductor 14 is an oxide film, 15 is a gate insulating film, and 16 is a gate electrode.

Claims (1)

[Claims] Mask regions (12, 12') on a semiconductor substrate (11)
anisotropically etching the substrate by providing an inclined surface (11a) created by the anisotropic etching;
a step of growing a semiconductor layer (13) of a conductivity type opposite to that of the substrate on the substrate (11) having a substrate, and a step of planarizing the semiconductor layer 13. A method of manufacturing a semiconductor device in which a region (11b) of the substrate sandwiched between inclined surfaces (11a) is used as a channel region.