JPH0330307B2 - - Google Patents
Info
- Publication number
- JPH0330307B2 JPH0330307B2 JP61229714A JP22971486A JPH0330307B2 JP H0330307 B2 JPH0330307 B2 JP H0330307B2 JP 61229714 A JP61229714 A JP 61229714A JP 22971486 A JP22971486 A JP 22971486A JP H0330307 B2 JPH0330307 B2 JP H0330307B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- mosfet
- semiconductor substrate
- type
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 37
- 238000009792 diffusion process Methods 0.000 claims description 23
- 238000002955 isolation Methods 0.000 description 15
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はMOS型半導体装置に係り、特にその
素子分離構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device, and particularly to an element isolation structure thereof.
（従来の技術）
従来のMOS型半導体装置の一例としてCMOS
型半導体装置を第４図に示す。例えば一部表面に
Ｎ型ウエル領域２が形成されているＰ型半導体基
板１にそれぞれＰ型半導体基板１表面にはＮチヤ
ネルMOSFET３が、Ｎ型ウエル領域２表面には
ＰチヤネルMOSFET４が形成されている。Ｎチ
ヤネルMOSFET３はＮ型不純物が拡散されたソ
ース・ドレイン領域８とこのソース・ドレイン間
の基板１表面上に形成されたゲート電極９とから
成つており、またＰチヤネルMOSFET４はウエ
ル領域２の表面近くに形成され、Ｐ型不純物が拡
散されたソースドレイン領域１０とこのソース・
ドレイン間のウエル領域２の表面上に形成された
ゲート電極１１とから成つている。Ｎ型ウエル領
域２にはウエル電位を固定するための拡散領域５
が設けられ、ウエル領域２と半導体基板１との表
面付近の境界には、ウエル領域２と拡散領域８と
を分離するウエル分離領域６がMOSFET３，４
及び拡散領域５の各々の間には、素子分離領域７
が設けられている。(Conventional technology) CMOS is an example of a conventional MOS type semiconductor device.
A type semiconductor device is shown in FIG. For example, in a P-type semiconductor substrate 1 having an N-type well region 2 formed on a part of its surface, an N-channel MOSFET 3 is formed on the surface of the P-type semiconductor substrate 1, and a P-channel MOSFET 4 is formed on the surface of the N-type well region 2. There is. The N-channel MOSFET 3 consists of a source/drain region 8 in which N-type impurities are diffused and a gate electrode 9 formed on the surface of the substrate 1 between the source and drain. This source/drain region 10 is formed nearby and has P-type impurities diffused into it.
A gate electrode 11 is formed on the surface of the well region 2 between the drains. The N-type well region 2 has a diffusion region 5 for fixing the well potential.
A well isolation region 6 is provided at the boundary near the surface of the well region 2 and the semiconductor substrate 1 to separate the well region 2 and the diffusion region 8.
Between each of the diffusion regions 5 and 5, an element isolation region 7 is provided.
is provided.
このようなCMOS型半導体装置はラツチアツ
プや素子間の導通等の異常な電荷の動作を防止す
るためにウエル分離領域６及び素子分離領域７は
充分に大きく形成する必要がある。しかし、集積
化微細化が望まれる装置ではウエル分離領域６及
び素子分離領域７を大きく形成することができな
いという問題がある。 In such a CMOS type semiconductor device, the well isolation region 6 and the element isolation region 7 must be formed sufficiently large to prevent abnormal charge operations such as latch-up and conduction between elements. However, in a device in which integration and miniaturization are desired, there is a problem in that the well isolation region 6 and the element isolation region 7 cannot be formed large.
（発明が解決しようとする問題点）
一般にMOS半導体装置では電界の異常動作を
防止するために素子分離領域及びウエル分離領域
を大きく形成することが望まれるが、従来の
MOS半導体装置では、MOS型トランジスタ素子
が形成される領域以外の素子分離領域やウエル分
離領域を充分大きく形成すると、半導体装置の平
面の面積が大きくなり微細化に適したMOS半導
体装置を形成することが困難である。(Problems to be Solved by the Invention) Generally, in MOS semiconductor devices, it is desirable to form large element isolation regions and well isolation regions in order to prevent abnormal operation of the electric field.
In a MOS semiconductor device, if the element isolation region and well isolation region other than the region where the MOS transistor element is formed are formed sufficiently large, the planar area of the semiconductor device increases, making it possible to form a MOS semiconductor device suitable for miniaturization. is difficult.
本発明ではウエル領域、素子領域を充分に分離
させ、かつ、微細化に適したMOS型半導体装置
を提供することを目的とする。 An object of the present invention is to provide a MOS type semiconductor device in which a well region and an element region are sufficiently separated and which is suitable for miniaturization.
（問題点を解決するための手段）
本発明の半導体装置はMOSFETのソース・ド
レイン領域及びウエル領域が表面に形成された半
導体基板に部分的にソース・ドレイン領域及びウ
エル領域よりも深く段差が形成されており、この
段差の下段面と上段面上とにはそれぞれMOS型
トランジスタが形成されており、段差側壁には絶
縁領域が形成されていることを特徴とする。
(Means for Solving the Problems) In the semiconductor device of the present invention, a step is partially formed deeper than the source/drain region and the well region in a semiconductor substrate on which the source/drain region and the well region of the MOSFET are formed. MOS transistors are formed on the lower and upper surfaces of the step, respectively, and an insulating region is formed on the sidewall of the step.
（作用）
本発明のように、表面にウエル領域及び
MOSFETのソース・ドレイン領域が形成された
半導体基板にウエル領域及びMOSFETのソース
ドレイン領域より深い段差を設け、半導体基板の
上段部表面と下段部表面上とにそれぞれ
MOSFETを形成し、段部側面に絶縁領域を設け
たことにより、従来、表面上に広く設けられてい
たウエル分離領域素子分離領域等が基板の厚さ方
向に延びる領域に設けられ、完全にウエル領域、
拡散領域、各領域を分離する。(Function) As in the present invention, a well region and a
A step deeper than the well region and the source/drain region of the MOSFET is provided in the semiconductor substrate on which the source/drain regions of the MOSFET are formed, and a step is formed on the upper surface and the lower surface of the semiconductor substrate, respectively.
By forming a MOSFET and providing an insulating region on the side surface of the step, the well isolation region, element isolation region, etc., which were conventionally provided widely on the surface, are now provided in a region extending in the thickness direction of the substrate, and the well isolation region is completely covered. region,
Diffusion area, separate each area.
（実施例）
本発明のCMOS半導体装置に適用した一実施
例を第１図を用いて説明する。(Example) An example applied to a CMOS semiconductor device of the present invention will be described with reference to FIG.
Ｎ型半導体基板２１表面にＰ型ウエル領域２２
を形成した後（第１図ａ図示）、凹部２３を形成
するためのレジストパターンを形成し、これをマ
スクとしてRIE法によりウエル領域２２より深く
異方性エツチングを行ない凹部２３を形成する
（第１図ｂ図示）。凹部２３の底面及び一部側面は
半導体基板２１が露出している。 A P-type well region 22 is formed on the surface of the N-type semiconductor substrate 21.
After forming the resist pattern (as shown in FIG. 1A), a resist pattern for forming the recess 23 is formed, and using this as a mask, anisotropic etching is performed deeper than the well region 22 by the RIE method to form the recess 23. (Illustrated in Figure 1b). The semiconductor substrate 21 is exposed at the bottom and some side surfaces of the recess 23 .
この半導体基板の凹部を形成するための他の方
法として高濃度のＮ型半導体基板の凹部を形成し
ようとする領域上に酸化膜を形成した後、この高
濃度Ｎ型半導体基板上に選択的にエピタキシヤル
成長させてＰ型領域を形成する。酸化膜上にはエ
ピタキシヤル成長はしないので凹部を形成する領
域以外の領域にＰ型領域が形成される。このエピ
タキシヤル成長ではＮ型基板表面上に直接Ｐ型領
域は成長せず、多少基板よりは濃度の低いＮ型領
域が成長した上にＰ型領域が形成される。次に酸
化膜を除去すると第１図ｂに示すようなＮ型領域
上に形成されたＰ型領域より深い凹部を有する半
導体基板が得られ、これを用いてもよい。 Another method for forming recesses in a semiconductor substrate is to form an oxide film on a region of a highly doped N-type semiconductor substrate where a recess is to be formed, and then selectively deposit the oxide film on the highly doped N-type semiconductor substrate. A P-type region is formed by epitaxial growth. Since no epitaxial growth occurs on the oxide film, a P-type region is formed in a region other than the region where the recess is to be formed. In this epitaxial growth, a P-type region does not grow directly on the surface of an N-type substrate, but a P-type region is formed on top of an N-type region grown with a concentration somewhat lower than that of the substrate. Next, by removing the oxide film, a semiconductor substrate having a recess deeper than the P-type region formed on the N-type region as shown in FIG. 1B is obtained, and this may be used.
次に凹部２３を含む半導体基板２１及びウエル
領域２２表面にSiO2のような酸化膜２４を推積
させ（第１図Ｃ図示）、再びRIE法により凹部２
３側壁の酸化膜２５を残こしてエツチング除去す
る（第１図ｄ図示）。次にＰ型ウエル領域２２表
面にＮチヤネル型MOSFETのゲート電極２６と
ソース・ドレイン領域となるＮ型拡散層２７とを
形成する。一方、凹部２３の底部のＮ型半導体基
板２１表面にＰチヤネル型MOSFETのゲート電
極２８と、ソース・ドレイン領域となるＰ型拡散
層２９とを形成する。このようにして第１図ｅに
示すようなウエル領域２２の表面に形成されたＮ
チヤネル型MOSFET３０と、ウエル領域２２よ
り深く形成された凹部２３の底面に露出した半導
体基板２１の表面上に形成されたＰチヤネル型
MOSFET３１と、これらＮチヤネル型
MOSFET３０とＰチヤネル型MOSFET３１と
の間の凹部側壁にウエル領域２２と拡散領域２９
とを分離する酸化膜層２５とからなるCMOS型
半導体装置が得られる。 Next, an oxide film 24 such as SiO 2 is deposited on the surfaces of the semiconductor substrate 21 and the well region 22 including the recesses 23 (as shown in FIG.
The oxide film 25 on the third side wall is removed by etching, leaving it (as shown in FIG. 1d). Next, on the surface of the P-type well region 22, a gate electrode 26 of an N-channel MOSFET and an N-type diffusion layer 27 which will become the source/drain region are formed. On the other hand, on the surface of the N-type semiconductor substrate 21 at the bottom of the recess 23, a gate electrode 28 of a P-channel MOSFET and a P-type diffusion layer 29 which will become a source/drain region are formed. In this way, N is formed on the surface of the well region 22 as shown in FIG. 1e.
A channel type MOSFET 30 and a P channel type MOSFET formed on the surface of the semiconductor substrate 21 exposed at the bottom of the recess 23 formed deeper than the well region 22.
MOSFET31 and these N-channel type
A well region 22 and a diffusion region 29 are formed on the side wall of the recess between the MOSFET 30 and the P-channel MOSFET 31.
A CMOS type semiconductor device is obtained, which comprises an oxide film layer 25 separating the two.
このような、CMOS型半導体装置は、従来、
ウエル領域と拡散領域とを分離する領域が表面の
拡がる方向に形成されていたのに対して、半導体
基板に設けられた凹部の側面すなわち基板表面と
垂直に拡がる方向に形成されているので、表面積
を大きくとることなく、ウエル領域と拡散領域と
を十分に分離することができる。また凹部側面に
設けた絶縁体は、凹部底面上に形成する
MOSFETのソース・ドレイン領域を形成するマ
スクとして働くので、このソース・ドレイン領域
を自己整合的に決めることができ、PEP（写真食
刻工程）等により形成したソース・ドレイン領域
と比べマスク合わせによる位置ずれがなく加工精
度が向上し、微細化に適する。 Conventionally, such CMOS type semiconductor devices
Whereas the region separating the well region and the diffusion region was formed in the direction in which the surface spreads, the region that separates the well region and the diffusion region is formed in the direction that extends perpendicularly to the side surface of the recess provided in the semiconductor substrate, that is, the substrate surface. The well region and the diffusion region can be sufficiently separated without increasing the distance. Also, the insulator provided on the side of the recess should be formed on the bottom of the recess.
Since it works as a mask to form the source/drain regions of MOSFETs, these source/drain regions can be determined in a self-aligned manner, and compared to source/drain regions formed by PEP (photo-etching process), etc., the positions are determined by mask alignment. There is no deviation, improving machining accuracy, making it suitable for miniaturization.
次に他の実施例を第２図及び第３図に示す。第
２図に示した実施例は半導体基板４１に３段にわ
たつて段差が形成されており、その最上段部とな
る半導体基板４１上にウエル領域４２が形成さ
れ、その表面にゲート電極４３、ソース・ドレイ
ン領域４４からなるMOSFET４５が形成されて
いる。中段部はウエル領域４２より深く半導体基
板４１中に設けられ、MOSFET４６のソース・
ドレイン領域となる拡散層４７が中段部表面に設
けられている。上段部と中段部との境の段部側壁
５２にはSiO2からなる絶縁層４８が設けられ、
ウエル領域４２と拡散層４７とを分離している。
中段部と下段部との境の段部側壁５３にはSiO2
４９を介してMOSFET４６のゲート電極５０が
形成され、このゲート電極５０と、下段部表面に
設けられたソースまたはドレイン領域となる拡散
層５１及び中段部表面の拡散層４７とで、側壁５
３を活性領域とするMOSFET４６が形成されて
いる。 Next, other embodiments are shown in FIGS. 2 and 3. In the embodiment shown in FIG. 2, three steps are formed on a semiconductor substrate 41, and a well region 42 is formed on the semiconductor substrate 41, which is the uppermost step, and a gate electrode 43 is formed on the surface of the well region 42. A MOSFET 45 consisting of source/drain regions 44 is formed. The middle portion is provided deeper in the semiconductor substrate 41 than the well region 42, and serves as the source/metal of the MOSFET 46.
A diffusion layer 47 serving as a drain region is provided on the surface of the middle portion. An insulating layer 48 made of SiO 2 is provided on the step side wall 52 at the boundary between the upper step and the middle step.
The well region 42 and the diffusion layer 47 are separated.
SiO 2 is applied to the step side wall 53 at the boundary between the middle step and the lower step.
A gate electrode 50 of the MOSFET 46 is formed through the MOSFET 49, and this gate electrode 50, a diffusion layer 51 serving as a source or drain region provided on the surface of the lower stage, and a diffusion layer 47 on the surface of the middle stage form the sidewall 5.
A MOSFET 46 having active region 3 is formed.
第３図に示した実施例はウエル領域６２が表面
に形成された半導体基板６１に４段にわたつて段
差が設けられている。ウエル領域６２には２段に
わたつて段差が形成されており、上段と下段のそ
れぞれ表面にMOSFET６３のソース・ドレイン
領域６４が形成され、上段と下段の間の段部側壁
７１にMOSFET６３のゲート酸化膜を介してゲ
ート電極６５が形成されている。また、ウエル領
域６２より深い半導体基板６１中には２段にわた
る段差が形成されており、この段部の上段及び下
段の表面にはMOSFET６６のソース・ドレイン
領域となる拡散層６７が形成され、上段と下段と
の間の段部側壁７２にSiO2６８を介して
MOSFET６６のゲート電極６９が形成されてい
る。ウエル領域６２に形成されたMOSFET６２
と半導体基板６１に形成されたMOSFET６６と
の境の段差側壁７３にはSiO2からなる絶縁層７
０が形成されている。このように第３図の実施例
は、段差側壁に活性領域をもつMOSFETが、そ
れぞれ半導体基板とウエル領域とに設けられ、そ
の境界の段差側壁に絶縁層が形成された構造の半
導体装置である。 In the embodiment shown in FIG. 3, a semiconductor substrate 61 having a well region 62 formed on its surface is provided with four steps. A step is formed in the well region 62 in two steps, and a source/drain region 64 of the MOSFET 63 is formed on the surface of each of the upper and lower steps, and a gate oxidation layer of the MOSFET 63 is formed on the step sidewall 71 between the upper and lower steps. A gate electrode 65 is formed through the film. Furthermore, a two-step step is formed in the semiconductor substrate 61 deeper than the well region 62, and a diffusion layer 67 that becomes the source/drain region of the MOSFET 66 is formed on the surface of the upper and lower steps of this step. and the lower step through SiO 2 68 on the step side wall 72.
A gate electrode 69 of the MOSFET 66 is formed. MOSFET 62 formed in the well region 62
An insulating layer 7 made of SiO 2 is formed on a step side wall 73 at the boundary between the MOSFET 66 formed on the semiconductor substrate 61 and the MOSFET 66 formed on the semiconductor substrate 61.
0 is formed. As described above, the embodiment shown in FIG. 3 is a semiconductor device having a structure in which MOSFETs having active regions on the side walls of the step are provided in the semiconductor substrate and the well region, respectively, and an insulating layer is formed on the side wall of the step at the boundary. .
第３図及び第４図に示した様な実施例ではウエ
ル領域と拡散領域とを分離する領域を半導体基板
の段差側壁に設けたうえにMOSFETのゲート電
極を段差側壁に設けているので更に微細化が可能
である。 In the embodiments shown in FIGS. 3 and 4, the region separating the well region and the diffusion region is provided on the side wall of the step of the semiconductor substrate, and the gate electrode of the MOSFET is provided on the side wall of the step, making it even finer. It is possible to
本実施例では、段差側壁にSiO2を形成してウ
エル領域と拡散領域を分離しているが、SiO2に
限定されることはなく絶縁性のあるものであれば
SiO2以外のものでもよい。また半導体基板はＮ
型に限られることはない。さらに、本実施例は
CMOS型半導体装置で述べているがCMOS型に
限定されないことは言うまでもない。 In this example, SiO 2 is formed on the step sidewall to separate the well region and the diffusion region, but the material is not limited to SiO 2 and any insulating material may be used.
It may be other than SiO 2 . Also, the semiconductor substrate is N
It is not limited to the type. Furthermore, this example
Although the description refers to a CMOS type semiconductor device, it goes without saying that the invention is not limited to the CMOS type.
本発明によれば半導体基板の表面積を大きくし
ないで、ラツチアツプ等の電界の異常動作を防止
するためのウエル分離領域を大きく形成すること
ができるので、信頼性が高く微細化に適した半導
体装置が得られる。
According to the present invention, it is possible to form a large well isolation region for preventing abnormal electric field operations such as latch-up without increasing the surface area of the semiconductor substrate, so a semiconductor device with high reliability and suitable for miniaturization can be obtained. can get.
第１図は本発明の一実施例、第２図及び第３図
は本発明の他の実施例、第４図は従来技術の例を
示す。
２１……半導体基板、２２……ウエル領域、２
５……凹部側壁絶縁層、２６，２８……ゲート電
極、２７，２９……拡散層、３０，３１……
MOSFET。
FIG. 1 shows one embodiment of the present invention, FIGS. 2 and 3 show other embodiments of the invention, and FIG. 4 shows an example of the prior art. 21... Semiconductor substrate, 22... Well region, 2
5... Concave side wall insulating layer, 26, 28... Gate electrode, 27, 29... Diffusion layer, 30, 31...
MOSFET.
Claims (1)
接し、この第１領域表面より低い表面を有する第
２領域とを有する半導体基板と、 前記第１領域表面の段差部側端部に形成された
段差部より浅いソース又はドレイン領域となる拡
散領域を有する第１のMOSFETと、 前記第１領域の段差部側端部に前記拡散領域の
裏面に隣接する様形成された半導体領域と、 前記第２領域表面に形成されたソース又はドレ
イン領域となる拡散領域を有する第２の
MOSFETと、 前記半導体基板の段差部の側壁で且つ前記第２
領域上に形成された絶縁領域とを有することを特
徴とする半導体装置。 ２ 第１領域とこの第１領域と段差部を介して隣
接し、この第１領域表面より低い表面を有する第
２領域とを有する一導電型半導体基板と、 前記第１領域表面の段差部側端部に形成された
段差部より浅い他導電型のウエル領域と、 前記第１領域表面の段差部側端部に形成された
前記ウエル領域より浅いソース又はドレイン領域
となる拡散領域を有する一導電型MOSFETと、
前記第２領域表面に形成されたソース又はドレイ
ン領域となる拡散領域を有する他導電型
MOSFETと、 前記半導体基板の段差部の側壁で且つ前記第２
領域上に形成された絶縁領域とを有することを特
徴とする半導体装置。[Scope of Claims] 1. A semiconductor substrate having a first region and a second region adjacent to the first region via a step portion and having a surface lower than the surface of the first region; a first MOSFET having a diffusion region forming a source or drain region shallower than the step formed at an end of the step; and a first MOSFET formed at an end of the step of the first region so as to be adjacent to the back surface of the diffusion region. a second semiconductor region having a diffusion region formed on a surface of the second region and serving as a source or drain region;
MOSFET, and a side wall of the stepped portion of the semiconductor substrate and the second
What is claimed is: 1. A semiconductor device comprising: an insulating region formed over the region; 2. A semiconductor substrate of one conductivity type having a first region and a second region adjacent to the first region via a step portion and having a surface lower than the surface of the first region; and a side of the step portion of the surface of the first region. a well region of a different conductivity type shallower than the step portion formed at the end portion; and a diffusion region forming a source or drain region shallower than the well region formed at the end portion of the surface of the first region on the side of the step portion. type MOSFET,
another conductivity type having a diffusion region forming a source or drain region formed on the surface of the second region;
MOSFET, and a side wall of the stepped portion of the semiconductor substrate and the second
What is claimed is: 1. A semiconductor device comprising: an insulating region formed over the region;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229714A JPS6386467A (en) | 1986-09-30 | 1986-09-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61229714A JPS6386467A (en) | 1986-09-30 | 1986-09-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6386467A JPS6386467A (en) | 1988-04-16 |
| JPH0330307B2 true JPH0330307B2 (en) | 1991-04-26 |
Family
ID=16896549
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61229714A Granted JPS6386467A (en) | 1986-09-30 | 1986-09-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6386467A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100511930B1 (en) * | 1998-12-16 | 2005-10-26 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| JP2007294857A (en) * | 2006-03-28 | 2007-11-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56133844A (en) * | 1980-03-22 | 1981-10-20 | Toshiba Corp | Semiconductor device |
| JPS5730342A (en) * | 1980-07-30 | 1982-02-18 | Toshiba Corp | Manufacture of semiconductor device |
-
1986
- 1986-09-30 JP JP61229714A patent/JPS6386467A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56133844A (en) * | 1980-03-22 | 1981-10-20 | Toshiba Corp | Semiconductor device |
| JPS5730342A (en) * | 1980-07-30 | 1982-02-18 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6386467A (en) | 1988-04-16 |
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