JP2511399B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2511399B2 JP2511399B2 JP60133616A JP13361685A JP2511399B2 JP 2511399 B2 JP2511399 B2 JP 2511399B2 JP 60133616 A JP60133616 A JP 60133616A JP 13361685 A JP13361685 A JP 13361685A JP 2511399 B2 JP2511399 B2 JP 2511399B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- conductivity
- transistor
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 21
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 claims 2
- 239000010408 film Substances 0.000 description 71
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- 238000000034 method Methods 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、相補型縦型半導体装置の製造方法に関す
る。The present invention relates to a method for manufacturing a complementary vertical semiconductor device.
（従来技術とその問題点） シリコンのMOS（Metal−Oxide−Semiconductor）トラ
ンジスタは、シリコン基板の表面を熱酸化してゲート酸
化膜（ゲート絶縁膜）とし、その上にドープした（ある
いは、最終的にはドープされることになる）多結晶シリ
コン膜を堆積したあとパターニングし、同一面内にゲー
ト、ソース、ドレインを形成するという方法で製造され
ている。従つて、１つの素子が平面的に３つの領域から
なること、コンタクト・ホールの形成において２つ以上
の領域が接触しないようにするために目合わせマージン
をとる必要があることなどから素子の微細化にはおのず
と限界があつた。特に近年素子の微細化が進むと、ゲー
トの面積とかコンタクト・ホールの面積とかに較べると
揺かに本質的でない要素によつて微細化が阻まれること
になつている。(Prior art and its problems) In a silicon MOS (Metal-Oxide-Semiconductor) transistor, the surface of a silicon substrate is thermally oxidized to form a gate oxide film (gate insulating film), and the gate oxide film (or final It is manufactured by a method of depositing a polycrystalline silicon film and patterning it to form a gate, a source and a drain in the same plane. Therefore, one element is composed of three regions in plan view, and it is necessary to provide a margin for alignment in order to prevent two or more regions from contacting each other when forming a contact hole. There was a natural limit to the conversion. In particular, as devices have been miniaturized in recent years, miniaturization has been hindered by factors that are not essential compared to the area of gates and the area of contact holes.
それに対する１つの解決策として、ジヤーナル・オブ
・クリスタル・グロース（J.Cryst.Growth）63巻1983
年,493〜526ページに記載されているように、選択エピ
タキシヤル成長法を用いた縦型MOSトランジスタの提案
がある。提案されている構造を第４図に示す。製造工程
は特に示されていないが、推定すると以下のようにな
る。まず、シリコン基板30を熱酸化し表面にSiO231を形
成し、その上に不純物をドープした多結晶のシリコン膜
32を堆積し、更にその上にSiO2膜33を形成したあと、部
分的にシリコン基板を露出させる。そのあと熱酸化（あ
るいはCVD法）によりSiO2膜を全面に形成したあと反応
性イオンエツチングによつて側壁部だけにSiO2膜34を残
す。そのあとシリコン基板が露出した領域だけに選択的
にシリコンエピタキシヤル成長層35を形成する。しかし
ながら、シリコンのデバイス・プロセスではSiO2の薄膜
を非常に多用する（表面保護や洗浄などにSiO2薄膜の形
成と除去は頻繁に用いられる）から、第４図の構造では
ゲート絶縁膜（SiO234）がなくなつたり、破れたり、部
分的に薄くなつたりするという欠点があつた。また、反
応性イオンエツチングによつて損傷をうけたあるいはカ
ーボンなどによつて汚染されたシリコン基板表面の回復
処理としては、いまのところ、シリコン基板表面を熱酸
化し、形成されたSiO2薄膜を除去することが最も有効で
ある。その処理法を用いると第４図の構造ではゲート絶
縁膜の厚さが制御できないという欠点もあつた。また、
第４図の構造では、多結晶シリコン膜32からなるゲート
が各素子に個別に設けられるから、微細化に限界があつ
た。One solution to this is the Journal of Crystal Growth, Vol. 63, 1983.
, Pp.493-526, there is a proposal for a vertical MOS transistor using the selective epitaxial growth method. The proposed structure is shown in FIG. Although the manufacturing process is not shown, it is estimated as follows. First, a silicon substrate 30 is thermally oxidized to form SiO 2 31 on the surface, and an impurity-doped polycrystalline silicon film is formed thereon.
After depositing 32 and further forming a SiO 2 film 33 thereon, the silicon substrate is partially exposed. After that, a SiO 2 film is formed on the entire surface by thermal oxidation (or a CVD method), and then the SiO 2 film 34 is left only on the side wall portion by reactive ion etching. After that, the silicon epitaxial growth layer 35 is selectively formed only in the exposed region of the silicon substrate. However, since the SiO 2 thin film is very often used in the silicon device process (the formation and removal of the SiO 2 thin film is frequently used for surface protection and cleaning), the structure of FIG. 2 34) was lost, torn, or partially thinned. In addition, as a recovery treatment for the surface of a silicon substrate that has been damaged by reactive ion etching or is contaminated by carbon, etc., for the moment, the surface of the silicon substrate is thermally oxidized and the formed SiO 2 thin film is removed. It is most effective to remove. If the processing method is used, the structure of FIG. 4 has a drawback that the thickness of the gate insulating film cannot be controlled. Also,
In the structure shown in FIG. 4, since the gate made of the polycrystalline silicon film 32 is individually provided for each element, there is a limit to miniaturization.
そこで、本発明の目的は、従来法に見られるような欠
点のない半導体装置の製造方法の提供にあり、特に、隣
接する領域に縦型でゲートを共有するＰ型トランジスタ
とＮ型トランジスタとを形成することにより、高集積化
が可能な半導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device which does not have the drawbacks found in the conventional method. In particular, a P-type transistor and an N-type transistor sharing a vertical gate in adjacent regions are provided. It is to provide a method for manufacturing a semiconductor device which can be highly integrated by forming the semiconductor device.
（問題点を解決するための手段） 本発明の製造方法によって得られる構造を第１図に示
す。シリコン基板１に凹部２と凸部３を設けられてお
り、凹部２は選択エピタキシヤル成長膜４で埋められて
いる。凸部３と選択エピタキシヤル成長膜４は絶縁膜
５、導電性の膜６、絶縁膜７により分離されている。凸
部３と選択エピタキシヤル成長膜４とには導電型の異な
る第１及び第２の縦型トランジスタがそれぞれ形成され
ており、導電性の膜６が共通のゲート電極をなし、絶縁
膜５が第１の縦型トランジスタのゲート絶縁膜をなし、
絶縁膜７が第２の縦型トランジスタのゲート絶縁膜をな
しており、その第２の縦型トランジスタのゲート絶縁膜
７は窒化シリコン膜を主体としている。(Means for Solving Problems) A structure obtained by the manufacturing method of the present invention is shown in FIG. A silicon substrate 1 is provided with a concave portion 2 and a convex portion 3, and the concave portion 2 is filled with a selective epitaxial growth film 4. The convex portion 3 and the selective epitaxial growth film 4 are separated by an insulating film 5, a conductive film 6 and an insulating film 7. First and second vertical transistors having different conductivity types are respectively formed on the convex portion 3 and the selective epitaxial growth film 4, the conductive film 6 forms a common gate electrode, and the insulating film 5 is formed. Forming the gate insulating film of the first vertical transistor,
The insulating film 7 forms a gate insulating film of the second vertical transistor, and the gate insulating film 7 of the second vertical transistor is mainly composed of a silicon nitride film.
第２図（ａ）〜（ｈ）は本発明の製造方法の主要部分
を具体例に沿つて説明する図である。シリコン基板８上
全面に絶縁膜14を堆積し、凹部９とすべき部分の絶縁膜
14を除去し残った絶縁膜14をマスクに基板８をエッチン
グする（第２図（ａ））。2 (a) to 2 (h) are diagrams for explaining the main part of the manufacturing method of the present invention along with specific examples. The insulating film 14 is deposited on the entire surface of the silicon substrate 8 to form the recess 9 in the insulating film.
The substrate 8 is etched by using the insulating film 14 remaining after removing 14 as a mask (FIG. 2A).
次に、側壁を含めた全面に絶縁膜11、不純物をドープ
したポリシリコン、金属、シリサイド等の導電性の膜12
をこの順に積層する（第２図（ｂ））。絶縁膜11が後に
ゲート絶縁膜、導電性の膜12は後に相補型MISFETのゲー
ト電極となる。Next, the insulating film 11 and the conductive film 12 such as polysilicon doped with impurities, metal and silicide are formed on the entire surface including the side wall.
Are laminated in this order (FIG. 2 (b)). The insulating film 11 will later become the gate insulating film, and the conductive film 12 will later become the gate electrode of the complementary MISFET.
次いで、反応性イオンエッチングによって凹部９と凸
部10の上の導電性の膜12を除去することで、側壁部だけ
に導電性の膜12を残す（第２図（ｃ））。Then, the conductive film 12 on the concave portion 9 and the convex portion 10 is removed by reactive ion etching, so that the conductive film 12 is left only on the side wall portion (FIG. 2 (c)).
次に絶縁膜13を側壁を含めた全面に形成し（第２図
（ｄ））、反応性イオンエッチングによって側壁部だけ
に絶縁膜13を残す（第２図（ｅ））。Next, the insulating film 13 is formed on the entire surface including the side wall (FIG. 2 (d)), and the insulating film 13 is left only on the side wall by reactive ion etching (FIG. 2 (e)).
次いで、導電性の膜12の上端部を少しエッチングウす
る。このときシリコン基板も少しエッチングされる（第
２図（ｆ））。次いで、絶縁膜15を段差を含めた全面に
形成する。このとき、導電性の膜12の上端部は非常に狭
い溝になっているので、絶縁膜15が厚く形成される（第
２図（ｇ））。その後反応性イオンエッチングを施して
この上端部に絶縁膜15を残す。同時に側壁部にも絶縁膜
15が残る。絶縁膜13と15を合わせて、一方のMISFETのゲ
ート絶縁膜になる。次に、シリコン基板が露出した部分
に選択的にシリコンエピタキシャル層16を成長させる
（第２図（ｈ））。Then, the upper end of the conductive film 12 is slightly etched. At this time, the silicon substrate is also slightly etched (FIG. 2 (f)). Next, the insulating film 15 is formed on the entire surface including steps. At this time, since the upper end of the conductive film 12 is a very narrow groove, the insulating film 15 is formed thick (FIG. 2 (g)). Then, reactive ion etching is performed to leave the insulating film 15 on the upper end portion. At the same time, the insulating film on the side wall
15 remains. The insulating films 13 and 15 together form the gate insulating film of one MISFET. Next, the silicon epitaxial layer 16 is selectively grown on the exposed portion of the silicon substrate (FIG. 2 (h)).
（作用） 本願の製造方法は、基本的には、シリコン基板に凹部
を設け、その側壁部にゲートを形成することによつて、
ある導電型（たとえばＰ型）の縦型MIS（Metal−Insula
tor−Semiconductor）トランジスタを形成し、縦（深
さ）方向のチヤンネルをゲートに加える電圧によつてON
/OFFできる構造を形成するものである。更に、本願方法
では、凹部を選択エピタキシヤル成長膜で埋め、そこに
別の導電型（たとえばＮ型）の縦型MISトランジスタを
形成し、ゲートを共有したCMIS（Complementary−Metal
−Insulator−Semiconductor）トランジスタの形成して
いる。より詳細な説明は、実施例を用いて具体的に説明
する。(Operation) In the manufacturing method of the present application, basically, the recess is formed in the silicon substrate and the gate is formed on the side wall of the recess.
A certain conductivity type (for example, P type) vertical MIS (Metal-Insula)
(Tor-Semiconductor) transistor is formed and turned on by the voltage applied to the gate in the vertical (depth) direction channel.
It forms a structure that can be turned on / off. Further, in the method of the present application, the recess is filled with a selective epitaxial growth film, a vertical MIS transistor of another conductivity type (for example, N type) is formed therein, and a CMIS (Complementary-Metal) sharing a gate is formed.
-Insulator-Semiconductor) A transistor is formed. A more detailed description will be specifically described using examples.
（実施例） 本発明の第１の実施例を第３図（ａ），（ｂ）の工程
図を参照して説明する。本図（ａ）の構造は、シリコン
基板19の上に約2000Åのひ素を高濃度ドープしたエピタ
キシヤル膜20を成長し、更に約１ミクロンのボロンを低
濃度ドープしたエピタキシヤル膜21を成長し、表面にひ
素をイオン注入によつて高濃度ドープしたあと、表面に
約2000ÅのSiO2膜22をCVD法で堆積し、パターニング
し、反応性イオンエツチングによつて約13ミクロンのシ
リコンを除去して凹部23を形成し、第２図と同様にして
側壁部だけに絶縁膜24、ボロンを高濃度ドープした多結
晶シリコン膜25、絶縁膜13、絶縁膜15を順に形成した状
態を示している。従つて、凹部27には縦方向にNPN構造
ができている。絶縁膜24、13、15はSiO2でも可能である
が、プロセス的にはSi3N4のほうが良好な結果が得られ
た。第３図（ｂ）の構造は同図（ａ）の構造の形成につ
づいて、シリコン基板が露出した領域だけに選択的に30
00Åのシリコンエピタキシヤル成長層28を形成しボロン
を高濃度ドープし、更に選択エピタキシヤル成長膜29を
堆積し、リンを深くイオン注入し、ボロン浅くイオン注
入した状態を示す。従つて、選択エピタキシヤル成長領
域には縦方向にPNP構造ができている。そのあと配線を
行ない、ゲートを共有したCMIS構造ができあがる。(Embodiment) A first embodiment of the present invention will be described with reference to the process diagrams of FIGS. 3 (a) and 3 (b). In the structure shown in FIG. 1A, an epitaxial film 20 of approximately 2000 Å highly doped with arsenic is grown on a silicon substrate 19, and an epitaxial film 21 of lightly doped approximately 1 micron of boron is grown. After heavily doping arsenic on the surface by ion implantation, deposit about 2000Å SiO 2 film 22 on the surface by CVD method, pattern it, and remove about 13 micron silicon by reactive ion etching. 2 shows a state in which an insulating film 24, a polycrystalline silicon film 25 heavily doped with boron, an insulating film 13, and an insulating film 15 are sequentially formed only on the side wall part as in FIG. . Therefore, the recess 27 has an NPN structure in the vertical direction. The insulating films 24, 13, and 15 can be made of SiO 2 , but Si 3 N 4 is better in terms of process. Following the formation of the structure of FIG. 3 (a), the structure of FIG. 3 (b) selectively removes only the region where the silicon substrate is exposed.
A state is shown in which a 00 Å silicon epitaxial growth layer 28 is formed, boron is highly doped, a selective epitaxial growth film 29 is further deposited, phosphorus is deeply ion-implanted, and boron is shallowly ion-implanted. Therefore, a PNP structure is formed in the vertical direction in the selective epitaxial growth region. After that, wiring is done and a CMIS structure with a shared gate is completed.
（発明の効果） シリコンのMOSプロセスは微細化が進み、サブミクロ
ン・オーダーのサイズが問題となりつつある。しかし、
それに応じて高密度化が進んでいるわけではなく、目合
せマージン、コンタクトの大きさなど、必ずしも本質的
ではない要素によつて高密度化が阻まれている。本発明
は同一面内に形成されていたゲート、ソース、ドレイン
を縦（深さ）方向に形成することによつて素子面積の微
細化を計るものである。具体的にいえば、ゲート、ソー
ス、ドレインが同一面内に形成されていると、ソース
（あるいはドレイン）に対するコンタクトがゲートおよ
びドレイン（あるいはソース）に対して分離されていな
ければならず、したがつてマージンをとらなくてはなら
ないのに対し、ゲート、ソース、ドレインを縦方向に形
成すれば、表面にはソース（あるいはドレイン）だけし
か現われないため、その領域すべてをコンタクトとして
用いることができる。とくに本発明を適用したCMIS構造
では、互いに隣接するＮ−チヤンネルのトランジスタと
Ｐ−チヤンネルのトランジスタとがゲートを共通にする
から、素子の微細化に対し非常に有効である。(Effects of the Invention) The MOS process of silicon is becoming finer, and the size of the submicron order is becoming a problem. But,
The densification is not progressing accordingly, and the densification is prevented by non-essential elements such as alignment margin and contact size. The present invention aims to miniaturize the element area by forming the gate, the source and the drain formed in the same plane in the vertical (depth) direction. Specifically, if the gate, source, and drain are formed in the same plane, the contact for the source (or drain) must be separated from the gate and drain (or source). On the other hand, a margin must be taken, but when the gate, source, and drain are formed in the vertical direction, only the source (or drain) appears on the surface, so that the entire region can be used as a contact. Particularly, in the CMIS structure to which the present invention is applied, the N-channel transistor and the P-channel transistor which are adjacent to each other have the same gate, which is very effective for miniaturization of the device.
第１図は本発明の製造方法によって得られる構造の半導
体装置を示す断面図、第２図（ａ）ないし（ｈ）は本願
の第２の発明に対応した工程を示す図、第３図（ａ），
（ｂ）は本発明の一実施例の工程を示す図、第４図は従
来の縦型MOSトランジスタの構造を示す断面図である。 １…シリコン基板、２…凹部、３…凸部、４…選択エピ
タキシヤル成長膜、５…絶縁膜、６…導電性の膜、７…
絶縁膜、８…シリコン基板、９…凹部、10…凸部、11…
絶縁膜、12…導電性の膜、13…絶縁膜、14…絶縁膜、15
…絶縁膜、16…シリコンエピタキシヤル成長層、17…シ
リコンの領域、18…シリコンの領域、19…シリコン基
板、20…エピタキシヤル膜、21…エピタキシヤル膜、22
…SiO2膜、23…凹部、24…絶縁膜、25…多結晶シリコン
膜、27…凸部、28…シリコンエピタキシヤル成長層、29
…選択エピタキシヤル成長膜、30…シリコン基板、31…
SiO2、32…多結晶のシリコン膜、33…SiO2膜、34…SiO2
膜、35…シリコンエピタキシヤル成長層。FIG. 1 is a cross-sectional view showing a semiconductor device having a structure obtained by the manufacturing method of the present invention, FIGS. 2 (a) to (h) are views showing steps corresponding to the second invention of the present application, and FIG. a),
(B) is a diagram showing a process of one embodiment of the present invention, and FIG. 4 is a sectional view showing a structure of a conventional vertical MOS transistor. 1 ... Silicon substrate, 2 ... Recessed portion, 3 ... Convex portion, 4 ... Selective epitaxial growth film, 5 ... Insulating film, 6 ... Conductive film, 7 ...
Insulating film, 8 ... Silicon substrate, 9 ... Recessed portion, 10 ... Convex portion, 11 ...
Insulating film, 12 ... Conductive film, 13 ... Insulating film, 14 ... Insulating film, 15
... Insulating film, 16 ... Silicon epitaxial growth layer, 17 ... Silicon area, 18 ... Silicon area, 19 ... Silicon substrate, 20 ... Epitaxy film, 21 ... Epitaxy film, 22
... SiO 2 film, 23 ... recessed part, 24 ... insulating film, 25 ... polycrystalline silicon film, 27 ... projected part, 28 ... silicon epitaxial growth layer, 29
… Selective epitaxial growth film, 30… Silicon substrate, 31…
SiO 2 , 32 ... Polycrystalline silicon film, 33 ... SiO 2 film, 34 ... SiO 2
Film, 35 ... Silicon epitaxial growth layer.
Claims (1)
る第１導電型層、このトランジスタのチャネル領域とな
る第２導電型層、このトランジスタのもう一方の拡散層
となる第１導電型層がこの順に積層されたシリコン基板
に対し、深い方の第１導電型層より深くエッチングして
基板に段差を形成する工程と、全面に、第１のゲート絶
縁膜、相補型MISトランジスタのゲート電極となる導電
性の膜を形成し次いでエッチングしてこれらの膜を段差
の側壁部分にのみ残す工程と、第２のゲート絶縁膜を全
面に形成し次いでエッチングして段差の側壁部分にのみ
残す工程と、エッチングされた部分の基板上に、第２導
電型、第１導電型、第２導電型のエピタキシャル成長層
を積層して第２導電型MISトランジスタとする工程と、
を含むことを特徴とする相補型MIS半導体装置の製造方
法。1. A first conductivity type layer serving as a diffusion layer of a first conductivity type MIS transistor, a second conductivity type layer serving as a channel region of this transistor, and a first conductivity type layer serving as another diffusion layer of this transistor. On the silicon substrate laminated in this order to form a step on the substrate by etching deeper than the deeper first conductivity type layer, and the first gate insulating film and the gate electrode of the complementary MIS transistor on the entire surface. Of forming a conductive film to be used as a mask and then etching the film to leave these films only on the sidewalls of the step, and a step of forming a second gate insulating film on the entire surface and then etching the film to leave only the sidewalls of the step. And a step of stacking second-conductivity-type, first-conductivity-type, and second-conductivity-type epitaxial growth layers on the etched portion of the substrate to form a second-conductivity-type MIS transistor,
A method of manufacturing a complementary MIS semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133616A JP2511399B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60133616A JP2511399B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61292357A JPS61292357A (en) | 1986-12-23 |
| JP2511399B2 true JP2511399B2 (en) | 1996-06-26 |
Family
ID=15108978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60133616A Expired - Lifetime JP2511399B2 (en) | 1985-06-19 | 1985-06-19 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2511399B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0687500B2 (en) * | 1987-03-26 | 1994-11-02 | 日本電気株式会社 | Semiconductor memory device and manufacturing method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562257U (en) * | 1979-06-18 | 1981-01-10 | ||
| JPS61263257A (en) * | 1985-05-17 | 1986-11-21 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1985
- 1985-06-19 JP JP60133616A patent/JP2511399B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61292357A (en) | 1986-12-23 |
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