JPS5730342A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5730342A JPS5730342A JP10447680A JP10447680A JPS5730342A JP S5730342 A JPS5730342 A JP S5730342A JP 10447680 A JP10447680 A JP 10447680A JP 10447680 A JP10447680 A JP 10447680A JP S5730342 A JPS5730342 A JP S5730342A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- stepped section
- semiconductor substrate
- etching
- 1mum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
Abstract
PURPOSE:To bring the level measurements of an element isolation region to zero and to contrive high density integration by a method wherein a stepped section is provided by performing an etching on a semiconductor substrate and a field oxide film is formed vertically on the inner wall of the stepped section. CONSTITUTION:The pattern of an Si oxide film 2 of 1mum in thickness is formed on the Si semiconductor substrate 1, a reactive ion etching is performed using the above pattern as a mask and the stepped section 15 of 1mum in depth is formed on the semiconductor substrate 1. Then, after the Si oxide film has been removed, an ion is implanted vertically on a proton and a donor layer 16 is formed on the upper surface of the semiconductor substrate 1 and on the bottom surface of the stepped section 15. Subsequently, when anode formation is performed, no current is applied to the donor layer 16, anode is formed only on P type inner wall 15a of the stepped section 15 and a porous Si layer 17 is formed. Lastly, when a wet thermal oxidization is performed and the thin oxide film formed on the surface is removed by etching, element forming regions 7a-7c which are isolated by a field oxide film 5 can be obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10447680A JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10447680A JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5730342A true JPS5730342A (en) | 1982-02-18 |
JPS6117144B2 JPS6117144B2 (en) | 1986-05-06 |
Family
ID=14381616
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10447680A Granted JPS5730342A (en) | 1980-07-30 | 1980-07-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5730342A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6386467A (en) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | Semiconductor device |
JP2007294857A (en) * | 2006-03-28 | 2007-11-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
-
1980
- 1980-07-30 JP JP10447680A patent/JPS5730342A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6386467A (en) * | 1986-09-30 | 1988-04-16 | Toshiba Corp | Semiconductor device |
JPH0330307B2 (en) * | 1986-09-30 | 1991-04-26 | ||
JP2007294857A (en) * | 2006-03-28 | 2007-11-08 | Elpida Memory Inc | Semiconductor device and manufacturing method therefor |
Also Published As
Publication number | Publication date |
---|---|
JPS6117144B2 (en) | 1986-05-06 |
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