JPS56115547A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56115547A
JPS56115547A JP1879080A JP1879080A JPS56115547A JP S56115547 A JPS56115547 A JP S56115547A JP 1879080 A JP1879080 A JP 1879080A JP 1879080 A JP1879080 A JP 1879080A JP S56115547 A JPS56115547 A JP S56115547A
Authority
JP
Japan
Prior art keywords
injected
hole
insulator regions
different
sio2 layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1879080A
Other languages
Japanese (ja)
Inventor
Kazumasa Nawata
Yuichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1879080A priority Critical patent/JPS56115547A/en
Publication of JPS56115547A publication Critical patent/JPS56115547A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose

Abstract

PURPOSE:To simultaneously form insulator regions having different depths used to isolate an element by forming ion implantation layers having different depths using mask layers having different thickness according to the place formed on a semiconductor substrate and heat treating them. CONSTITUTION:Holes 14, 15 are opened at an Si substrate 11 covered with an SiO2 layer 12 and an Si3N4 layer 13. In the hole 14 the SiO2 layer is also removed, but in the hole 15 the SiO2 layer is retained. When oxygen ions are injected thereto, they are injected deeply to the hole 14 and injected shallowly to the hole 15. Thereafter, this is thermally oxidized to rapidly oxidize the region where the oxygen ions are injected, and insulator regions having different depth can be formed. Thus, the insulator regions having different depth can be formed by one step.
JP1879080A 1980-02-18 1980-02-18 Manufacture of semiconductor device Pending JPS56115547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1879080A JPS56115547A (en) 1980-02-18 1980-02-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1879080A JPS56115547A (en) 1980-02-18 1980-02-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56115547A true JPS56115547A (en) 1981-09-10

Family

ID=11981395

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1879080A Pending JPS56115547A (en) 1980-02-18 1980-02-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56115547A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097637A (en) * 1983-11-01 1985-05-31 Matsushita Electronics Corp Manufacture of semiconductor device
US4564583A (en) * 1983-02-07 1986-01-14 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
DE4212503A1 (en) * 1991-04-15 1992-10-22 Gold Star Electronics SEMICONDUCTOR MODULE AND METHOD FOR THE PRODUCTION THEREOF
US6127242A (en) * 1994-02-10 2000-10-03 Micron Technology, Inc. Method for semiconductor device isolation using oxygen and nitrogen ion implantations to reduce lateral encroachment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4564583A (en) * 1983-02-07 1986-01-14 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
JPS6097637A (en) * 1983-11-01 1985-05-31 Matsushita Electronics Corp Manufacture of semiconductor device
US5116775A (en) * 1986-06-18 1992-05-26 Hitachi, Ltd. Method of producing semiconductor memory device with buried barrier layer
DE4212503A1 (en) * 1991-04-15 1992-10-22 Gold Star Electronics SEMICONDUCTOR MODULE AND METHOD FOR THE PRODUCTION THEREOF
US5182226A (en) * 1991-04-15 1993-01-26 Gold Star Electron Co., Ltd. Method for fabrication of a field oxide of the buried inverse t-type using oxygen or nitrogen ion implantation
US6127242A (en) * 1994-02-10 2000-10-03 Micron Technology, Inc. Method for semiconductor device isolation using oxygen and nitrogen ion implantations to reduce lateral encroachment

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