JPS56148825A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56148825A
JPS56148825A JP5247780A JP5247780A JPS56148825A JP S56148825 A JPS56148825 A JP S56148825A JP 5247780 A JP5247780 A JP 5247780A JP 5247780 A JP5247780 A JP 5247780A JP S56148825 A JPS56148825 A JP S56148825A
Authority
JP
Japan
Prior art keywords
opening
layer
polycrystal
oxide film
margins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5247780A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Tanahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5247780A priority Critical patent/JPS56148825A/en
Publication of JPS56148825A publication Critical patent/JPS56148825A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form two electrodes without needing margins by a method wherein polycrystal Si is made up to an opening of an electrode layer with the opening, an exposed surface thereof built up on a semiconductor substrate is coated with an oxide film, and impurities are diffused through the layer. CONSTITUTION:An oxide film 2, polycrystal Si 3 and an oxide film 7 are laminated on a semiconductor substrate 1, an opening reaching to the substrate is formed by utilizing photoresist, N ions are injected using the photoresist as a mask and a Si3N4 film is made up on the surface, a wall surface of the opening is coated with the oxide film by means of thermal oxidation, the Si3N4 film is removed, a polycrystal Si layer 10 is built up to the opening, impurities are diffused throgh the Si layer 10 and a diffusion layer 11 is formed. Thus, a polycrystal Si gate electrode and an electrode extracted from the diffusion layer can be formed independently without needing margins.
JP5247780A 1980-04-21 1980-04-21 Manufacture of semiconductor device Pending JPS56148825A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5247780A JPS56148825A (en) 1980-04-21 1980-04-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5247780A JPS56148825A (en) 1980-04-21 1980-04-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56148825A true JPS56148825A (en) 1981-11-18

Family

ID=12915796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5247780A Pending JPS56148825A (en) 1980-04-21 1980-04-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56148825A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245148A (en) * 1984-05-18 1985-12-04 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5354710A (en) * 1988-01-14 1994-10-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices using an adsorption enhancement layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53132275A (en) * 1977-04-25 1978-11-17 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and its production

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60245148A (en) * 1984-05-18 1985-12-04 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5354710A (en) * 1988-01-14 1994-10-11 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices using an adsorption enhancement layer

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