JPS5456357A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5456357A
JPS5456357A JP12235877A JP12235877A JPS5456357A JP S5456357 A JPS5456357 A JP S5456357A JP 12235877 A JP12235877 A JP 12235877A JP 12235877 A JP12235877 A JP 12235877A JP S5456357 A JPS5456357 A JP S5456357A
Authority
JP
Japan
Prior art keywords
layer
film
mask
oxide film
annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12235877A
Other languages
Japanese (ja)
Inventor
Katsumi Ogiue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12235877A priority Critical patent/JPS5456357A/en
Priority to US05/931,007 priority patent/US4219369A/en
Priority to DE19782840975 priority patent/DE2840975A1/en
Publication of JPS5456357A publication Critical patent/JPS5456357A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)

Abstract

PURPOSE: To produce a device of small element sizes by forming the opposite conductivity type layer formed on substrate front to island form by etching grooves and performing enlarged diffusion.
CONSTITUTION: After an N+ layer 2 and an oxide film 3 are made on P type Si, etching grooves 5 are provided through a nitride film mask 4, isolating the N+ layer 2 in island form. P+ ion implanted layers 6 are created only in the groove bottom by making use of the eaves 4' of the the mask, after which annealing is performed. When the films 4, 3 are removed and an N layer 8 is made, the N+ layer 2 and P+ layer 6 diffuse in the layer 8. Next, masks 13 by oxide film 11 and nitride film 12 are selectively formed, after which an oxide film 14 is made. The film 14 is selectively opened and N+ layers 16 are made down to the layer 2. Next, B ions are implanted to create a P layer 17 through self-alignment. After annealing in N2, the surface is covered with PSG 18 and further a phosphorus doped viscous glass film 19 is spin-coated to flatten the grooves. Next, the films 19, 18, 14 are opened, an N+ layer 20 is provided and electrode windows 20, 23 are selectively formed, to which electrodes are attached. Since this method eliminates the need for mask margins and does not produce any bird heads, the scale of integration may be increased
COPYRIGHT: (C)1979,JPO&Japio
JP12235877A 1977-09-30 1977-10-14 Production of semiconductor device Pending JPS5456357A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP12235877A JPS5456357A (en) 1977-10-14 1977-10-14 Production of semiconductor device
US05/931,007 US4219369A (en) 1977-09-30 1978-08-04 Method of making semiconductor integrated circuit device
DE19782840975 DE2840975A1 (en) 1977-09-30 1978-09-20 METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12235877A JPS5456357A (en) 1977-10-14 1977-10-14 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5456357A true JPS5456357A (en) 1979-05-07

Family

ID=14833913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12235877A Pending JPS5456357A (en) 1977-09-30 1977-10-14 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5456357A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613743A (en) * 1979-07-16 1981-02-10 Fujitsu Ltd Semiconductor device and its manufacture
JPS5630737A (en) * 1979-08-21 1981-03-27 Seiko Epson Corp Semiconductor ic circuit
JPS5879752A (en) * 1981-11-06 1983-05-13 Hitachi Ltd Semiconductor device
JPH01134914A (en) * 1987-11-20 1989-05-26 Fujitsu Ltd Manufacture of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5613743A (en) * 1979-07-16 1981-02-10 Fujitsu Ltd Semiconductor device and its manufacture
JPS5630737A (en) * 1979-08-21 1981-03-27 Seiko Epson Corp Semiconductor ic circuit
JPH0147010B2 (en) * 1979-08-21 1989-10-12 Seiko Epson Corp
JPS5879752A (en) * 1981-11-06 1983-05-13 Hitachi Ltd Semiconductor device
JPH0512863B2 (en) * 1981-11-06 1993-02-19 Hitachi Ltd
JPH01134914A (en) * 1987-11-20 1989-05-26 Fujitsu Ltd Manufacture of semiconductor device

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