JPS5556646A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5556646A
JPS5556646A JP13015278A JP13015278A JPS5556646A JP S5556646 A JPS5556646 A JP S5556646A JP 13015278 A JP13015278 A JP 13015278A JP 13015278 A JP13015278 A JP 13015278A JP S5556646 A JPS5556646 A JP S5556646A
Authority
JP
Japan
Prior art keywords
phosphor
sio
heat treatment
psg
sapphire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13015278A
Other languages
Japanese (ja)
Other versions
JPS594864B2 (en
Inventor
Nobuo Sasaki
Yasuo Kobayashi
Takashi Iwai
Motoo Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53130152A priority Critical patent/JPS594864B2/en
Publication of JPS5556646A publication Critical patent/JPS5556646A/en
Publication of JPS594864B2 publication Critical patent/JPS594864B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the lowering of the mobility of a SOS device, by obstructing the diffusion of phosphor to the source and drain layers of a p channel element from PSG by means of an extremely simple means, and by executing heat treatment of every kind in an amalgamated shape.
CONSTITUTION: Poly-Si gate electrodes 4 are manufactured on Si islands 2a, 2b on sapphire 1 by resist masks 6 through SiO23. Ions are injected to n and p channel elements q2, q1 by successively using resist masks 7, 8, and a p+-layer to the island 2a and an n+ gate electrode and an n+ layer to the island 2b. The sapphire is coated with PSG5, electrode windows 5a'5B are produced, phosphor is injected to layers 4 in non-additional shapes at the p channel element Q1 side when softening the whole by means of heat tratment and n+ gate electrodes are formed. Lastly, SiO23 exposed to the windows 5aW5d is etched. Al wiring 6aW6d are manufactured and the wiring is covered with the PSG. Thus, the undesirable diffusion of phosphor and the lowering of the mobility of a SOS device can be prevented because the SiO2 films 3 are beforehand left, multi-purpose is accomplished by means of one heat treatment and the time of heat treatment is shortened.
COPYRIGHT: (C)1980,JPO&Japio
JP53130152A 1978-10-23 1978-10-23 Manufacturing method for semiconductor devices Expired JPS594864B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53130152A JPS594864B2 (en) 1978-10-23 1978-10-23 Manufacturing method for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53130152A JPS594864B2 (en) 1978-10-23 1978-10-23 Manufacturing method for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5556646A true JPS5556646A (en) 1980-04-25
JPS594864B2 JPS594864B2 (en) 1984-02-01

Family

ID=15027219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53130152A Expired JPS594864B2 (en) 1978-10-23 1978-10-23 Manufacturing method for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS594864B2 (en)

Also Published As

Publication number Publication date
JPS594864B2 (en) 1984-02-01

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