JPS5783059A - Manufacture of mos type semiconductor device - Google Patents
Manufacture of mos type semiconductor deviceInfo
- Publication number
- JPS5783059A JPS5783059A JP15854880A JP15854880A JPS5783059A JP S5783059 A JPS5783059 A JP S5783059A JP 15854880 A JP15854880 A JP 15854880A JP 15854880 A JP15854880 A JP 15854880A JP S5783059 A JPS5783059 A JP S5783059A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- implanted
- channel region
- polycrystalline
- ion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract 2
- 229910052760 oxygen Inorganic materials 0.000 abstract 2
- 239000001301 oxygen Substances 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To form the element of buried gate structure for the subject semiconductor device by a method wherein a semiconductor layer is provided on the substrate, on which a reverse conductive layer was formed on the surface, through the intermediary of an insulating film, and two kinds of ion implanting processes are performed using a channel region as a mask. CONSTITUTION:An oxide film 2 is provided on a P type substrate 1, and after an N<+> layer 3 has been implanted on the above, a P type polycrystalline Si layer 4 is laminated. Then, a resist mask 5 is provided in an expected channel region, a high density of oxygen, for example, is ion-implanted in the N<+> layer 3, and subsequently As, for example, is ion-implanted in the polycrystalline Si layer 4. Then, the mask 5 is removed, a heat-treatment is performed, a gate electrode 7 is formed by turning the oxygen implanted section into an SiO2 film, and at the same time, the As implanted section is activated to an N<+> type. Subsequently, a patterning is performed on the polycrystalline Si layer, and a self- matched channel region 8 is laid out on the source and drain regions 9 and 10 and the gate electrode 7. Through procedures, a buried gate structure can be formed microscopically.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854880A JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15854880A JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5783059A true JPS5783059A (en) | 1982-05-24 |
| JPS6244819B2 JPS6244819B2 (en) | 1987-09-22 |
Family
ID=15674108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15854880A Granted JPS5783059A (en) | 1980-11-11 | 1980-11-11 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5783059A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182570A (en) * | 1983-03-31 | 1984-10-17 | Fujitsu Ltd | Semiconductor device |
| JPS63112124A (en) * | 1986-10-31 | 1988-05-17 | Nippon Zeon Co Ltd | Method for reaction injection molding |
| JPH05211166A (en) * | 1991-12-02 | 1993-08-20 | Nec Corp | Thin film field-effect trasistor |
| WO2001097290A3 (en) * | 2000-06-16 | 2002-08-15 | Advanced Micro Devices Inc | Buried inverted gate field-effect transistor (bigfet) |
-
1980
- 1980-11-11 JP JP15854880A patent/JPS5783059A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182570A (en) * | 1983-03-31 | 1984-10-17 | Fujitsu Ltd | Semiconductor device |
| JPS63112124A (en) * | 1986-10-31 | 1988-05-17 | Nippon Zeon Co Ltd | Method for reaction injection molding |
| JPH0729320B2 (en) * | 1986-10-31 | 1995-04-05 | 日本ゼオン株式会社 | Reaction injection molding method |
| JPH05211166A (en) * | 1991-12-02 | 1993-08-20 | Nec Corp | Thin film field-effect trasistor |
| WO2001097290A3 (en) * | 2000-06-16 | 2002-08-15 | Advanced Micro Devices Inc | Buried inverted gate field-effect transistor (bigfet) |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6244819B2 (en) | 1987-09-22 |
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