JPS5710262A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5710262A
JPS5710262A JP8473080A JP8473080A JPS5710262A JP S5710262 A JPS5710262 A JP S5710262A JP 8473080 A JP8473080 A JP 8473080A JP 8473080 A JP8473080 A JP 8473080A JP S5710262 A JPS5710262 A JP S5710262A
Authority
JP
Japan
Prior art keywords
implanted
region
thickness
film
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8473080A
Other languages
Japanese (ja)
Other versions
JPS6355220B2 (en
Inventor
Junichi Yoshinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP8473080A priority Critical patent/JPS5710262A/en
Publication of JPS5710262A publication Critical patent/JPS5710262A/en
Publication of JPS6355220B2 publication Critical patent/JPS6355220B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain highly integrated circuit in a process for forming source and drain region in a complementary MOSIC, by selecting ion energy to be implanted in each channel and the thickness of the oxide film on the surface of each implanted region. CONSTITUTION:A P type well region 3 is provided in an N type substrate, and an SiO2 film 2 having the thickness of 4,000Angstrom is formed on the surface. Then the film 2 at the P channel source and drain regions is removed, and an SiO2 having the thickness of about 1,000Angstrom is grown again. Then, B ions 7 are implanted, e.g., at 70KeV. Windows are opened in the N channel region, and phosphorus ions 9 are implanted, e.g., at 30KeV. After the surface layer of the ion implanted SiO2 film is removed, heat treatment is performed, implanted layers 8 and 10 are activated, and sources and drains 11 and 12 for both P and N channels are concurrently formed. In this method, since the process is simplified, and the number of heat treatment is decreased, spread in the lateral direction of the source and drain can be reduced, and the highly integrated device can be obtained.
JP8473080A 1980-06-23 1980-06-23 Manufacture of semiconductor device Granted JPS5710262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8473080A JPS5710262A (en) 1980-06-23 1980-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8473080A JPS5710262A (en) 1980-06-23 1980-06-23 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5710262A true JPS5710262A (en) 1982-01-19
JPS6355220B2 JPS6355220B2 (en) 1988-11-01

Family

ID=13838802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8473080A Granted JPS5710262A (en) 1980-06-23 1980-06-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5710262A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219221A (en) * 1989-02-20 1990-08-31 Rohm Co Ltd Manufacture of semiconductor device
JPH08130252A (en) * 1994-11-02 1996-05-21 Nec Corp Fabrication of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267281A (en) * 1975-12-01 1977-06-03 Seiko Epson Corp Semiconductor unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5267281A (en) * 1975-12-01 1977-06-03 Seiko Epson Corp Semiconductor unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02219221A (en) * 1989-02-20 1990-08-31 Rohm Co Ltd Manufacture of semiconductor device
JPH08130252A (en) * 1994-11-02 1996-05-21 Nec Corp Fabrication of semiconductor device

Also Published As

Publication number Publication date
JPS6355220B2 (en) 1988-11-01

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