JPS5783061A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS5783061A JPS5783061A JP15869480A JP15869480A JPS5783061A JP S5783061 A JPS5783061 A JP S5783061A JP 15869480 A JP15869480 A JP 15869480A JP 15869480 A JP15869480 A JP 15869480A JP S5783061 A JPS5783061 A JP S5783061A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- ion
- gate
- nitriding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000005121 nitriding Methods 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 239000011229 interlayer Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 239000002184 metal Substances 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To contrive high integration and high speed operation for the subject semiconductor integrated circuit by a method wherein, on the gate electrode consisting of high melting point metal, an ion implanted mask, which is slightly smaller than the gate electrode, is provided and a source and drain region is formed by implantation. CONSTITUTION:A gate film 2 is formed on the FET forming region on a P type substrate 1, for example, and after an Mo film 3 and an Si nitriding film 4 have been deposited, for example, a photoetching is performed in such a manner that the films 3 and 4 will be remained on the gate region. The shape of this nitriding film pattern 4 is formed approximately 0.2-0.5mum smaller than the Mo film pattern 3 which will be used as a gate electrode. Then, through an Mo film 3, N type impurities are ion-implanted using the energy with which a little ion will reach the substrate, and a source and drain regions 5 and 6, where the lower part of the Mo film unmasked by the nitriding film 4 was formed in shallow low density, are formed. Subsequently, an interlayer film 7 and electrode wirings 8 and 9 are provided and used as an FET, and through these procedures, the shortening of the effective channel length caused by the expansion diffusion layer and the increase of a parasitic capacity can be prevented, thereby enabling to obtain a microscopically formed element which can be operated at a high speed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15869480A JPS5783061A (en) | 1980-11-11 | 1980-11-11 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15869480A JPS5783061A (en) | 1980-11-11 | 1980-11-11 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5783061A true JPS5783061A (en) | 1982-05-24 |
Family
ID=15677306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15869480A Pending JPS5783061A (en) | 1980-11-11 | 1980-11-11 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5783061A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122273A (en) * | 1985-11-22 | 1987-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
-
1980
- 1980-11-11 JP JP15869480A patent/JPS5783061A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122273A (en) * | 1985-11-22 | 1987-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
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