JPS5748268A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS5748268A JPS5748268A JP55122410A JP12241080A JPS5748268A JP S5748268 A JPS5748268 A JP S5748268A JP 55122410 A JP55122410 A JP 55122410A JP 12241080 A JP12241080 A JP 12241080A JP S5748268 A JPS5748268 A JP S5748268A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- drain
- thickness
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 3
- 239000012535 impurity Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
PURPOSE:To reduce resistance of an Mo film and to prevent reduction of power gain of an MOS semiconductor device by a method wherein the upper part of an Mo gate is covered with a polycrystalline silicon layer, and heat treatment is performed. CONSTITUTION:An Si substrate 1 is thermally oxidized to form a gate oxide film 2 on the surface. An Mo film of about 4,500Angstrom thickness is formed on the gate oxide film 2, and photo resist treatment and sputter etching are performed to form the Mo gate 3. Impurity ions are implanted therein for formation of source and drain masking the Mo gate. Si is made to be accumulated by the vapor phase growth method to form the polycrystalline Si layer 11 of about 1,000Angstrom thickness on the whole surface. A PSG film 6 of about 7,000Angstrom thickness is formed in succession. After then annealing is performed in N2 atmosphere at 600 deg.C for 20min or more to make the impurity to be diffused in the Si substrate to form a source 4 and a drain 5. PSG, polycrystalline Si on the surface of the gate part, the source and drain, are etched selectively to expose the contact parts. At this time, the surface of the Mo film is slightly etched to remove the oxide layer on the surface. Then an Al electrode 7 is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122410A JPS5748268A (en) | 1980-09-05 | 1980-09-05 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55122410A JPS5748268A (en) | 1980-09-05 | 1980-09-05 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5748268A true JPS5748268A (en) | 1982-03-19 |
Family
ID=14835109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55122410A Pending JPS5748268A (en) | 1980-09-05 | 1980-09-05 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5748268A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57166077A (en) * | 1981-04-07 | 1982-10-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| WO2006061369A1 (en) * | 2004-12-06 | 2006-06-15 | Infineon Technologies Ag | Semiconductor device and method of manufacture thereof |
| US7429777B2 (en) | 2005-02-25 | 2008-09-30 | Kabushiki Kaisha Toshiba | Semiconductor device with a gate electrode having a laminate structure |
-
1980
- 1980-09-05 JP JP55122410A patent/JPS5748268A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57166077A (en) * | 1981-04-07 | 1982-10-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH0556026B2 (en) * | 1981-04-07 | 1993-08-18 | Matsushita Electric Ind Co Ltd | |
| WO2006061369A1 (en) * | 2004-12-06 | 2006-06-15 | Infineon Technologies Ag | Semiconductor device and method of manufacture thereof |
| US7291526B2 (en) | 2004-12-06 | 2007-11-06 | Infineon Technologies Ag | Semiconductor device and method of manufacture thereof |
| US7576399B2 (en) | 2004-12-06 | 2009-08-18 | Infineon Technologies Ag | Semiconductor device and method of manufacture thereof |
| US7429777B2 (en) | 2005-02-25 | 2008-09-30 | Kabushiki Kaisha Toshiba | Semiconductor device with a gate electrode having a laminate structure |
| US8592924B2 (en) | 2005-02-25 | 2013-11-26 | Kabushiki Kaisha Toshiba | Semiconductor device including gate electrode having a laminate structure and a plug electrically connected thereto |
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