JPS5690549A - Mos type semiconductor device and its manufacture - Google Patents
Mos type semiconductor device and its manufactureInfo
- Publication number
- JPS5690549A JPS5690549A JP16729979A JP16729979A JPS5690549A JP S5690549 A JPS5690549 A JP S5690549A JP 16729979 A JP16729979 A JP 16729979A JP 16729979 A JP16729979 A JP 16729979A JP S5690549 A JPS5690549 A JP S5690549A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- region
- built
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000010410 layer Substances 0.000 abstract 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000010438 heat treatment Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000002344 surface layer Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910052594 sapphire Inorganic materials 0.000 abstract 1
- 239000010980 sapphire Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Local Oxidation Of Silicon (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain an inverse conduction type high-resistance element in excellent controllability by a method wherein ions are injected, heat treatment is conducted and only the surface layer section is changed into an oxide film when the element is formed in the first conduction type semiconductor layer stacked on an insulating substrate. CONSTITUTION:A p<-> type Si layer 2 is stacked on a sapphire substrate 1, the whole is thermally treated and only the surface layer section is turned into an SiO2 film 3, and the film 3 is formed in a fixed shape using a Si3N4 film 4 as a mask. Etching is conducted employing the film 3 as a mask, the thickness of the exposed section of the end part of the layer 2 is thinned, an opening 5 is made up to the laminating films 4, 3, and ions are injected and an n<-> type region is built up in the layer 2. Heat treatment is conducted, a thick field SiO2 film 6 is built up at the end sections of layer 2 while the n<-> region is pushed down and an n<-> type high-resistance region 8 is formed, and a thick SiO2 film 7 is made up on the surface simultaneously. The films 4, 3 are removed, n<+> type source and drain and regions 12-14 for a power source terminal are built up in diffusion shapes in the layer 2 around the region 8, and a gate oxide film 11 is coated on a layer 2' between the regions 12 and 13.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16729979A JPS5690549A (en) | 1979-12-22 | 1979-12-22 | Mos type semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16729979A JPS5690549A (en) | 1979-12-22 | 1979-12-22 | Mos type semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5690549A true JPS5690549A (en) | 1981-07-22 |
Family
ID=15847171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16729979A Pending JPS5690549A (en) | 1979-12-22 | 1979-12-22 | Mos type semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5690549A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996025765A1 (en) * | 1995-02-16 | 1996-08-22 | Peregrine Semiconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon-on-sapphire |
| US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
| US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
| US5973363A (en) * | 1993-07-12 | 1999-10-26 | Peregrine Semiconductor Corp. | CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator |
-
1979
- 1979-12-22 JP JP16729979A patent/JPS5690549A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
| US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
| US5973363A (en) * | 1993-07-12 | 1999-10-26 | Peregrine Semiconductor Corp. | CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator |
| WO1996025765A1 (en) * | 1995-02-16 | 1996-08-22 | Peregrine Semiconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon-on-sapphire |
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