JPS5490978A - Manufacture for mos type semiconductor device - Google Patents

Manufacture for mos type semiconductor device

Info

Publication number
JPS5490978A
JPS5490978A JP15761477A JP15761477A JPS5490978A JP S5490978 A JPS5490978 A JP S5490978A JP 15761477 A JP15761477 A JP 15761477A JP 15761477 A JP15761477 A JP 15761477A JP S5490978 A JPS5490978 A JP S5490978A
Authority
JP
Japan
Prior art keywords
film
layer
coated
type
entire surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15761477A
Other languages
Japanese (ja)
Inventor
Shigeru Watari
Eisuke Ichinohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15761477A priority Critical patent/JPS5490978A/en
Publication of JPS5490978A publication Critical patent/JPS5490978A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To increase the dielectric strength performance, by making flat the element surface and by weakening the electric field between the gate electrode and the drain, through implanting thick insulation film at the part adjacent to the channel of the source and the drain region. CONSTITUTION:The SiO2 film 2 is coated on the P<-> type Si substrate 1, the opening 3 is made on the channel forming region of MOSFET, and the P type polycrystal Si layer having high impurity concentration than the substrate 1 is grown on the entire surface. Thus, the singlecrystal layer 4 is coated on the opening 3, the polycrystal layer 5 is produced on the film 2, the thin SiO2 film 8 is coated on the layer 4 and the thick SiO2 film 9 is coated on the layer 5, and the openings 6 and 7 are made on the film 9. Next, the N<+> type drain and source regions 11 and 12 are formed by depositing the N<+> type polycrystal film 10 on the entire surface and diffusing the impurity in it with heat treatment. After that, the entire surface is covered with the Si3N4 film 15, concaves 16 and 17 are provided at the both sides of the layer 4 with selective etching, heat treatment is made by taking the film 15 as a mask, the thick SiO2 films 18 and 19 are burried, and electrodes are respectively attached by removing the film 15.
JP15761477A 1977-12-28 1977-12-28 Manufacture for mos type semiconductor device Pending JPS5490978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15761477A JPS5490978A (en) 1977-12-28 1977-12-28 Manufacture for mos type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15761477A JPS5490978A (en) 1977-12-28 1977-12-28 Manufacture for mos type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5490978A true JPS5490978A (en) 1979-07-19

Family

ID=15653569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15761477A Pending JPS5490978A (en) 1977-12-28 1977-12-28 Manufacture for mos type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5490978A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610402U (en) * 1979-06-30 1981-01-29

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5610402U (en) * 1979-06-30 1981-01-29
JPS5848244Y2 (en) * 1979-06-30 1983-11-04 均 平野 Dust cup stand for "Chu" bunch

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