JPS57207375A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57207375A
JPS57207375A JP9183281A JP9183281A JPS57207375A JP S57207375 A JPS57207375 A JP S57207375A JP 9183281 A JP9183281 A JP 9183281A JP 9183281 A JP9183281 A JP 9183281A JP S57207375 A JPS57207375 A JP S57207375A
Authority
JP
Japan
Prior art keywords
film
polycrystal
patterned
films
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9183281A
Other languages
Japanese (ja)
Inventor
Tadatoshi Nozaki
Hidekazu Okabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9183281A priority Critical patent/JPS57207375A/en
Publication of JPS57207375A publication Critical patent/JPS57207375A/en
Pending legal-status Critical Current

Links

Classifications

    • H01L29/78

Abstract

PURPOSE:To obtain an MOS type FET having high threshold voltage by a method wherein a polycrystal Si film not doped and a silicide film are laminated and formed to the whole surface containing a gate oxide film with an opening, the silicide film is patterned, impurity ions are implanted in the polycrystal film exposed between the pattern, and source and drain regions are shaped through heat treatment while the polycrystal Si is changed into an oxide. CONSTITUTION:A thick field oxide film 32 is formed to the peripheral section of a P type Si substrate 31, the inside is coated with the thin gate oxide film 33, and the predetermined opening is shaped. The polycrystal Si film 34 to which an impurity is not doped intentionally and the Mo silicide film 35 are laminated and formed to the whole surface containing these films, and the film 35 is patterned and only gate electrode wiring and source and drain layer wiring are left. P Ions are implanted in the film 34 sections exposed between these wiring, the ions are diffused through heat treatment, the N type source and drain regions 36 are shaped while the films 34 on the regions are changed into the oxide 37, and sections between the films 35', 35'' patterned are insulated and isolated.
JP9183281A 1981-06-15 1981-06-15 Manufacture of semiconductor device Pending JPS57207375A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9183281A JPS57207375A (en) 1981-06-15 1981-06-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9183281A JPS57207375A (en) 1981-06-15 1981-06-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57207375A true JPS57207375A (en) 1982-12-20

Family

ID=14037566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9183281A Pending JPS57207375A (en) 1981-06-15 1981-06-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57207375A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653173A (en) * 1985-03-04 1987-03-31 Signetics Corporation Method of manufacturing an insulated gate field effect device

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