JPS5561069A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5561069A
JPS5561069A JP13389978A JP13389978A JPS5561069A JP S5561069 A JPS5561069 A JP S5561069A JP 13389978 A JP13389978 A JP 13389978A JP 13389978 A JP13389978 A JP 13389978A JP S5561069 A JPS5561069 A JP S5561069A
Authority
JP
Japan
Prior art keywords
layer
film
sio
type
grown
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13389978A
Other languages
Japanese (ja)
Inventor
Nobuo Sasaki
Yasuo Kobayashi
Takashi Iwai
Motoo Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13389978A priority Critical patent/JPS5561069A/en
Publication of JPS5561069A publication Critical patent/JPS5561069A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To increase voltage resistance, by having lowered the impurity concentration of the region sandwiching a gate electrode on a semiconductor substrate constituting SOS FET, and providing here high-concentration source and drain regions of opposite conduction type.
CONSTITUTION: Si epitaxial layer 1 is grown on sapphire substrate 20, and by etching, the thickness of areas 1a, 1b of the element-forming region is reduced by half. Next, SiO2 film 2 and Si3N4 film 3 are laminated on the element-forming region only. With this used as mask, heat treatment is operated, and layer 1 which is exposed in areas 1a and 1b is changed into SiO2, and its volume is expanded and its surface is made flat. Subsequently, films 2 and 3 are removed and exposed layer 1 is changed into p-type by ion injection; gate SiO2 film 6 and polycrystalline Si layer 7 are grown on its surface. Next, using resist film 8 as mask, layer 7 is etched and is retained as gate electrode 7. Film 8 is removed, p--type regions 13, 15 are provided on both sides of electrode 7 in layer 1 by ion injection, and here n+-type source and drain regions 11, 12 are formed.
COPYRIGHT: (C)1980,JPO&Japio
JP13389978A 1978-10-31 1978-10-31 Manufacture of semiconductor device Pending JPS5561069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13389978A JPS5561069A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13389978A JPS5561069A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5561069A true JPS5561069A (en) 1980-05-08

Family

ID=15115699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13389978A Pending JPS5561069A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5561069A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4797721A (en) * 1987-04-13 1989-01-10 General Electric Company Radiation hardened semiconductor device and method of making the same
US5316960A (en) * 1989-07-11 1994-05-31 Ricoh Company, Ltd. C-MOS thin film transistor device manufacturing method
US5477073A (en) * 1993-08-20 1995-12-19 Casio Computer Co., Ltd. Thin film semiconductor device including a driver and a matrix circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51102578A (en) * 1975-03-07 1976-09-10 Hitachi Ltd HANDOTAISOCHITOSONOSEIHO
JPS5283181A (en) * 1975-12-31 1977-07-11 Ibm Insulated gate fet transistor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51102578A (en) * 1975-03-07 1976-09-10 Hitachi Ltd HANDOTAISOCHITOSONOSEIHO
JPS5283181A (en) * 1975-12-31 1977-07-11 Ibm Insulated gate fet transistor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4797721A (en) * 1987-04-13 1989-01-10 General Electric Company Radiation hardened semiconductor device and method of making the same
US5316960A (en) * 1989-07-11 1994-05-31 Ricoh Company, Ltd. C-MOS thin film transistor device manufacturing method
US5477073A (en) * 1993-08-20 1995-12-19 Casio Computer Co., Ltd. Thin film semiconductor device including a driver and a matrix circuit
US5821137A (en) * 1993-08-20 1998-10-13 Casio Computer Co., Ltd. Thin film semiconductor device including a driver and a matrix circuit

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