JPS6412575A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS6412575A JPS6412575A JP16924287A JP16924287A JPS6412575A JP S6412575 A JPS6412575 A JP S6412575A JP 16924287 A JP16924287 A JP 16924287A JP 16924287 A JP16924287 A JP 16924287A JP S6412575 A JPS6412575 A JP S6412575A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrodes
- polycrystalline
- doped
- wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE:To reduce the resistance values of low impurity concentration source and drain diffused regions by a method wherein sidewalls made of polycrystalline Si doped with an impurity are formed on the side surfaces of a gate electrode and the impurity is diffused by a heat treatment to form the source and drain regions. CONSTITUTION:An element region with a gate oxide film 4 and an element isolation region with a field oxide film 3 are formed on a P-type semiconductor substrate 1. Then, gate electrodes 5A and 5B made of polycrystalline Si doped with phosphorus are formed on the film 4 and the film 3 respectively. Thick oxide films 6 are formed on the electrodes 5A and 5B. Then the film 4 is removed while the films 6 on the gate electrodes 5A and 5B are left. Then a phosphorus-doped polycrystalline Si film 7 is formed over the whole surface. Then side walls 7A and 7B are formed on the side surfaces of the electrodes 5A and 5B. After a photoresist film 8 is applied, the wall 7B is exposed. After the wall 7B and the resist film 8 are removed, N<+>type source and drain diffused layers 9 are formed by utilizing the electrode 5A and the wall 7A as a mask. Then N<->type source and drain regions 10 are formed by a heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16924287A JPH065679B2 (en) | 1987-07-06 | 1987-07-06 | Method for manufacturing MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16924287A JPH065679B2 (en) | 1987-07-06 | 1987-07-06 | Method for manufacturing MOS semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6412575A true JPS6412575A (en) | 1989-01-17 |
| JPH065679B2 JPH065679B2 (en) | 1994-01-19 |
Family
ID=15882877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16924287A Expired - Lifetime JPH065679B2 (en) | 1987-07-06 | 1987-07-06 | Method for manufacturing MOS semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065679B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742299A (en) * | 2016-05-16 | 2016-07-06 | 京东方科技集团股份有限公司 | Pixel unit as well as manufacturing method, array substrate and display device thereof |
-
1987
- 1987-07-06 JP JP16924287A patent/JPH065679B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742299A (en) * | 2016-05-16 | 2016-07-06 | 京东方科技集团股份有限公司 | Pixel unit as well as manufacturing method, array substrate and display device thereof |
| US10416515B2 (en) | 2016-05-16 | 2019-09-17 | Boe Technology Group Co., Ltd. | Pixel unit, array substrate, and display device, and fabrication methods thereof |
| CN105742299B (en) * | 2016-05-16 | 2019-11-29 | 京东方科技集团股份有限公司 | A kind of pixel unit and preparation method thereof, array substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH065679B2 (en) | 1994-01-19 |
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