JPS5649553A - Manufacture of semiconductor memory - Google Patents

Manufacture of semiconductor memory

Info

Publication number
JPS5649553A
JPS5649553A JP12412179A JP12412179A JPS5649553A JP S5649553 A JPS5649553 A JP S5649553A JP 12412179 A JP12412179 A JP 12412179A JP 12412179 A JP12412179 A JP 12412179A JP S5649553 A JPS5649553 A JP S5649553A
Authority
JP
Japan
Prior art keywords
film
capacity
oxide film
poly
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12412179A
Other languages
Japanese (ja)
Other versions
JPS6315748B2 (en
Inventor
Shinji Shimizu
Shinichiro Mitani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12412179A priority Critical patent/JPS5649553A/en
Publication of JPS5649553A publication Critical patent/JPS5649553A/en
Publication of JPS6315748B2 publication Critical patent/JPS6315748B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To reduce cell size by forming a capacity increasing P-N junction through self-matching by diffusing, through appropriate heat treatment, the different types of impurities on previously doped on an insulating film for capacity and a capacity electrode provided on the film. CONSTITUTION:A field oxide film 11 and an oxide film for capacity 12A are formed on the surface of a P type Si substrate and As ion is driven at a high density into the film 12A. SiO2 film 14A is formed by oxidizing the surface of poly-Si 13A fromed by CVD method. B ion is driven at a high density into the substrate with a resist mask 15 arranged. Advantageous therein is to expand grain by previously doping P on poly-Si. Next, an electrode 13 and insulating films 12 and 14 are formed by Hf-gas plasma etching and the surface of the substrate is exposed. An oxide film 14' amd a gate oxide film 12' are made by again making oxidation, and a poly-Si gate electrode 18 and ion drive-in layers 19 and 20 are formed. A P<+>-N<+> junction is formed of a capacity increasing p<+>-layer 16 and an N<+>-layer 17 made through heat treatment. Thereby, self-matching eliminates the necessity of mask adjustment allowance so that cell size can be reduced.
JP12412179A 1979-09-28 1979-09-28 Manufacture of semiconductor memory Granted JPS5649553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12412179A JPS5649553A (en) 1979-09-28 1979-09-28 Manufacture of semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12412179A JPS5649553A (en) 1979-09-28 1979-09-28 Manufacture of semiconductor memory

Publications (2)

Publication Number Publication Date
JPS5649553A true JPS5649553A (en) 1981-05-06
JPS6315748B2 JPS6315748B2 (en) 1988-04-06

Family

ID=14877435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12412179A Granted JPS5649553A (en) 1979-09-28 1979-09-28 Manufacture of semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5649553A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089436A (en) * 1987-09-21 1992-02-18 Samsung Semiconductor And Telecommunications Co., Ltd. Method for fabricating a semiconductor device by slope etching a polysiliow layer
US5120674A (en) * 1988-06-07 1992-06-09 Samsung Electronics Co., Ltd. Method of making stacked capacitor dram cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089436A (en) * 1987-09-21 1992-02-18 Samsung Semiconductor And Telecommunications Co., Ltd. Method for fabricating a semiconductor device by slope etching a polysiliow layer
US5120674A (en) * 1988-06-07 1992-06-09 Samsung Electronics Co., Ltd. Method of making stacked capacitor dram cell

Also Published As

Publication number Publication date
JPS6315748B2 (en) 1988-04-06

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