JPH065679B2 - Method for manufacturing MOS semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a MOS semiconductor device, and more particularly to a method for forming a source / drain diffusion layer of a high breakdown voltage MOS semiconductor device.

[Conventional technology]

Conventionally, this type of high withstand voltage MOS semiconductor device has been manufactured as shown in FIG.

First, as shown in FIG. 3A, the element region having the gate oxide film 4 and the field oxide film 3 on the semiconductor substrate 1A.
Then, an element isolation region is formed, and a gate electrode 5 made of polycrystalline silicon is formed.

Next, as shown in FIG. 3B, an impurity of the opposite conductivity type to the semiconductor substrate 1A is ion-implanted using the gate electrode 5 and the field oxide film 3 as a mask to form a low concentration source / drain diffusion layer 10A. .

Next, as shown in FIG. 3 (c), the gate electrode 5 is covered with a mask material 13 made of photoresist or the like, and an impurity having a conductivity type opposite to that of the semiconductor substrate 1A is ion-implanted to form a high concentration source / drain diffusion layer. 9A is formed.

Next, as shown in FIG. 3D, after removing the mask material 13, the interlayer insulating film 11 is formed, the contact hole is opened, and then the electrode wiring 12 made of Al is formed to form the MOS type semiconductor device. To complete.

[Problems to be solved by the invention]

In the conventional MOS semiconductor device described above, the wiring electrode 12
Since the shallow low-concentration source / drain diffusion layer 10A having a high resistance exists between the MOS transistor and the channel region of the MOS transistor, a large current cannot flow and the operation speed of the device becomes slow.

Further, in order to form the low concentration source / drain diffusion layer 10A between the wiring electrode 12 and the channel region of the MOS transistor, a photolithography process for selectively leaving the mask material 13 is required, and therefore the process is complicated. There is also a drawback that

An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device in which the resistance value of a low concentration source / drain diffusion layer is lowered and the speed is improved.

[Means for solving problems]

According to the present invention, a step of forming an element region having a gate oxide film and an element isolation region having a field oxide film on a semiconductor substrate of one conductivity type, and containing impurities on the gate oxide film and the field oxide film. Except for the step of forming the gate electrode and the gate wiring made of the first polycrystalline silicon, respectively, the step of oxidizing the gate electrode and the gate wiring to form an oxide film thicker than the gate oxide film on the surface thereof, except under the gate electrode. After removing the gate oxide film, a step of forming a second polycrystalline silicon film containing impurities of opposite conductivity type on the entire surface, and etching the second polycrystalline silicon film by anisotropic etching to form side surfaces of the gate electrode and the gate wiring. To the second
Of forming the side wall made of polycrystalline silicon, a step of applying a planarizing material made of an organic compound on the entire surface and then etching to expose the side wall of the side surface of the gate wiring, and a side wall of the side surface of the gate wiring by etching. A step of removing the planarizing material, a step of implanting ions of an opposite conductivity type impurity using the gate electrode and the side wall of the side surface thereof as a mask to form a high-concentration source / drain diffusion layer, and heat treatment A MOS characterized by including a step of diffusing impurities in a sidewall into a semiconductor substrate to form a low concentration source / drain diffusion layer, and a step of forming an insulating film over the entire surface of the semiconductor substrate including the sidewall. A method of manufacturing a semiconductor device is obtained. A photoresist may be used as the planarizing material.

〔Example〕

Next, the present invention will be described with reference to the drawings. 1 (a) to 1 (j) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and taken along the line AA 'in the plan view shown in FIG. It is a figure.

First, as shown in FIG. 1A, an element region having a thin gate oxide film 4 and an element isolation region having a field oxide film 3 and a channel stopper 2 are formed on a P-type semiconductor substrate 1. This gate oxide film 4 and field oxide film 3
A gate electrode 5A and a gate wiring 5B made of phosphorus-doped polycrystalline silicon are formed on the upper surface.

Next, as shown in FIG. 1 (b), low temperature wet oxidation (for example, 800 ° C. H ₂ —O ₂ treatment) is performed, and the surfaces of the gate electrode 5A and the gate wiring 5B are thickened using accelerated oxidation. The oxide film 6 is formed.

Next, as shown in FIG. 1 (c), the oxide film 6 on the surface of the gate electrode 5A and the gate wiring 5B is utilized by utilizing the difference in oxide film thickness.
Then, the gate oxide film 4 below the gate electrode 5A is removed by etching to expose the surface of the P-type semiconductor substrate 1.

Next, as shown in FIG. 1D, a second polycrystalline silicon film 7 doped with impurities such as phosphorus is formed over the entire surface.

Next, as shown in FIG. 1 (e), the second polycrystalline silicon 7 is etched by an anisotropic etching method, and the sidewalls 7 are formed on the side surfaces of the gate electrode 5A and the gate wiring 5B.
A and 7B are formed.

Next, as shown in FIG. 1 (f), a photoresist 8 is formed on the entire surface.
Is applied to the side wall 7 of the gate wiring 5B as shown in FIG. 1 (g).
Dip in developer until B is exposed.

Next, as shown in FIG. 1 (h), only the side wall 7B of the gate wiring 5B is removed by isotropic silicon etching, and then, as shown in FIG. 1 (i), a photoresist 8 is formed. Then, N-type impurities such as arsenic are implanted by an ion implantation method using the field oxide film 3, the gate electrode 5A and the sidewalls 7A as a mask to remove N ^+.
A source / drain diffusion layer 9 is formed. Then N ⁺
1000 for activation of the source / drain diffusion layer 9
℃ subjected to heat treatment, phosphorus is diffused from the sidewall 7A at the time of this heat treatment on the surface of the P-type semiconductor substrate 1 N ^-
The source / drain diffusion layer 10 is formed.

Thereafter, as shown in FIGS. 1 (j) and 2, an interlayer insulating film 11 made of PSG or the like is formed, contact holes are opened, and electrode wirings 12 are formed to complete a MOS type semiconductor device. .

As described above, according to this embodiment, the low-concentration source / drain diffusion layers of the transistor having the high breakdown voltage structure are formed on the side surface of the gate electrode of the transistor and are made of polycrystalline silicon directly connected to the semiconductor substrate. Since the sidewall and the N ⁻ type source / drain diffused layer formed by diffusing the sidewall into the semiconductor substrate are formed, the thickness of the source / drain diffused layer having a low concentration is substantially increased. This has the effect of reducing the increase in resistance value in the low-concentration source / drain diffusion layer, which has been a problem.

Further, since the high breakdown voltage structure which is conventionally required is formed, a lithography process for forming a mask material is not necessary.

〔The invention's effect〕

As described above, according to the present invention, a sidewall made of polycrystalline silicon containing impurities is formed on a side surface of a gate electrode, and a heat treatment is performed to diffuse the impurities in the sidewall into a semiconductor substrate to diffuse a low concentration of source / drain. By forming the layer, the source / drain diffusion layer having a substantially low concentration can be thickened, and thus the resistance value thereof can be reduced. Therefore, a MOS type semiconductor device having an improved operation speed can be obtained.

[Brief description of drawings]

1 (a) to 1 (j) are sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, FIG. 2 is a plan view of FIG. 1 (j), and FIG. a) to (d) are conventional M
FIG. 9 is a cross-sectional view of the semiconductor chip in the order of steps for explaining the method for manufacturing the OS semiconductor device. DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate, 1A ... Semiconductor substrate, 2 ... Channel stopper, 3 ... Field oxide film, 4 ... Gate oxide film, 5, 5A ... Gate electrode, 5B ... Gate wiring, 6 ...
Oxide film, 7 ... Second polycrystalline silicon, 7A, 7B ... Sidewall, 8 ... Photoresist, 9 ... N ⁺ type source
Drain diffusion layer, 9A ... High concentration source / drain diffusion layer, 10 ... N ⁻ type source / drain diffusion layer, 10A ... Low concentration source / drain diffusion layer, 11 ... Inter-layer insulating film, 12
... electrode wiring, 13 ... mask material.

Claims (2)

[Claims] 1. A step of forming an element region having a gate oxide film and an element isolation region having a field oxide film on one conductivity type semiconductor substrate, and containing impurities on the gate oxide film and the field oxide film. Forming a gate electrode and a gate wire made of a first polycrystalline silicon; oxidizing the gate electrode and the gate wire to form an oxide film thicker than the gate oxide film on the surface thereof; After removing the gate oxide film except underneath, forming a second polycrystalline silicon film containing impurities of opposite conductivity type on the entire surface, and etching the second polycrystalline silicon film by anisotropic etching A step of forming a side wall made of a second polycrystalline silicon on the side surfaces of the electrodes and the gate wiring, and applying a planarizing substance made of an organic compound on the entire surface. After that, the step of etching to expose the side wall of the side surface of the gate wiring, the step of removing the side wall of the side surface of the gate wiring by etching, and the step of removing the planarizing material and then the side wall of the gate electrode and its side surface are removed. A step of ion-implanting impurities of opposite conductivity type as a mask to form a high-concentration source / drain diffusion layer, and heat treatment to diffuse the impurities in the sidewalls into the semiconductor substrate to form a low-concentration source / drain layer.
A method of manufacturing a MOS semiconductor device, comprising: a step of forming a drain diffusion layer; and a step of forming an insulating film on the entire surface of the semiconductor substrate including the sidewalls. 2. The method for manufacturing a MOS type semiconductor device according to claim 1, wherein the planarizing material is photoresist.