JPS6348179B2 - - Google Patents
Info
- Publication number
- JPS6348179B2 JPS6348179B2 JP53152544A JP15254478A JPS6348179B2 JP S6348179 B2 JPS6348179 B2 JP S6348179B2 JP 53152544 A JP53152544 A JP 53152544A JP 15254478 A JP15254478 A JP 15254478A JP S6348179 B2 JPS6348179 B2 JP S6348179B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- substrate
- forming
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 24
- 229910052814 silicon oxide Inorganic materials 0.000 description 24
- 238000009792 diffusion process Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- XUIMIQQOPSSXEZ-OUBTZVSYSA-N silicon-29 atom Chemical compound [29Si] XUIMIQQOPSSXEZ-OUBTZVSYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/30—Nc systems
- G05B2219/39—Robotics, robotics to robotics hand
- G05B2219/39177—Compensation position working point as function of inclination tool, hand
Landscapes
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device.
従来の相補型絶縁ゲート型電界効果（CMOS）
半導体装置においては、Ｎ型基体の不純物濃度及
びＮ型基体上に形成されたＰ型ウエルの不純物濃
度によりMOSトランジスタのしきい値とフイー
ルド酸化膜領域の寄生MOSトランジスタのしき
い値はきまる。そして、MOSトランジスタの相
互コンダクタンスを大きくし、しきい値電圧を適
切なものたとえば0.5〜1.0Vとし、高速なものを
得ようとすると、Ｎ型基体及びＰ型ウエルの不純
物濃度を低くする必要があるためフイールド酸化
膜領域のしきい値電圧は低いものとなつてしま
う。しかるに現在ではCMOS半導体装置は低消
費電力という特長があるため広い応用範囲が期待
され、使用電圧が広く、かつ高速のCMOS集積
回路装置の要求が強まつている。MOSトランジ
スタのしきい値を基板濃度で決め、かつフイール
ド酸化膜領域の寄生MOSトランジスタのしきい
値を高くするためチヤンネルストツパを用いる方
法がある。この方法を特開昭52−86083による例
を一例として示す。 Traditional complementary insulated gate field effect (CMOS)
In a semiconductor device, the threshold value of a MOS transistor and the threshold value of a parasitic MOS transistor in a field oxide film region are determined by the impurity concentration of an N-type substrate and the impurity concentration of a P-type well formed on the N-type substrate. In order to increase the mutual conductance of the MOS transistor, set the threshold voltage to an appropriate level, for example 0.5 to 1.0V, and obtain a high-speed device, it is necessary to lower the impurity concentration of the N-type substrate and P-type well. Therefore, the threshold voltage of the field oxide film region becomes low. Nowadays, however, CMOS semiconductor devices are expected to have a wide range of applications because of their low power consumption, and there is an increasing demand for CMOS integrated circuit devices that can be used at a wide range of voltages and at high speeds. There is a method in which the threshold of the MOS transistor is determined by the substrate concentration and a channel stopper is used to increase the threshold of the parasitic MOS transistor in the field oxide film region. This method will be described as an example according to Japanese Patent Application Laid-Open No. 52-86083.
第１図ａ〜ｆには、従来の局部酸化（LOCOS）
構造でチヤンネルストツパを入れたＮ型基体上に
形成されるCMOS半導体装置の製造方法を示す。 Figures 1a-f show conventional local oxidation (LOCOS)
A method of manufacturing a CMOS semiconductor device formed on an N-type substrate with a channel stopper in its structure will be described.
まずＮ型半導体基体１の表面の一部に深さ8μ
ｍ程度のＰ型ウエル領域２を形成したのち、基体
１の表面を熱酸化して、うすい酸化シリコン膜３
を形成する。 First, a portion of the surface of the N-type semiconductor substrate 1 is placed at a depth of 8 μm.
After forming a P-type well region 2 with a thickness of about m, the surface of the substrate 1 is thermally oxidized to form a thin silicon oxide film 3.
form.
次に、この酸化シリコン膜３上の全面に窒化シ
リコン膜４を酸化シリコン膜３と同じ厚さ程度形
成する。（第１図ａ）
次に、フイールド酸化膜を形成する領域の上記
窒化シリコン被膜４およびこの膜下の酸化シリコ
ン膜３をフオトレジスト膜５をマスクにして除去
する。ついでＰチヤンネルトランジスタを形成す
る領域の基体１上をフオトレジスト膜６によつて
被覆し、Ｎチヤンネルトランジスタのフイールド
領域の基体表面にボロン等のＰ型不純物７をイオ
ン注入する（第１図ｂ）。 Next, a silicon nitride film 4 is formed on the entire surface of this silicon oxide film 3 to about the same thickness as the silicon oxide film 3. (FIG. 1a) Next, the silicon nitride film 4 in the region where the field oxide film is to be formed and the silicon oxide film 3 underneath this film are removed using the photoresist film 5 as a mask. Next, the substrate 1 in the region where the P-channel transistor is to be formed is covered with a photoresist film 6, and P-type impurities 7 such as boron are ion-implanted into the substrate surface in the field region of the N-channel transistor (FIG. 1b). .
この後上記フオトレジスト膜５，６を除去した
のちＮチヤンネルトランジスタを形成する領域の
基体１の表面に新たにフオトレジスト膜８を形成
する。次にＰウエル領域２を除く領域の基体１の
表面にリン等のドナー不純物９をイオン注入す
る。このとき、Ｐチヤンネルトランジスタの活性
領域にはうすい酸化シリコン膜とその上に同じ程
度厚さの窒化シリコン膜だけでマスクをするが、
加速電圧50keV〜70keVの低エネルギーでリン等
をイオン注入すれば、酸化シリコン膜の下にはつ
きぬけない。（第１図ｃ）。 Thereafter, after removing the photoresist films 5 and 6, a new photoresist film 8 is formed on the surface of the substrate 1 in the region where the N-channel transistor is to be formed. Next, a donor impurity 9 such as phosphorus is ion-implanted into the surface of the substrate 1 in a region excluding the P-well region 2. At this time, the active region of the P-channel transistor is masked with only a thin silicon oxide film and a silicon nitride film of approximately the same thickness on top of the thin silicon oxide film.
If ions such as phosphorus are implanted at a low energy acceleration voltage of 50 keV to 70 keV, they will not penetrate under the silicon oxide film. (Figure 1c).
次に上記フオトレジスト膜８を除去したのち、
水蒸気雰囲気中、1000℃の高温で、数時間の酸化
を行ない局部酸化（LOCOS）構造のフイールド
酸化シリコン膜１０を、1.0μｍ以上の厚さで形成
する。次に、上記選択酸化のマスクである難酸化
性被膜４およびその膜下の薄い酸化シリコン膜３
を除去する。（第１図ｄ）上記の選択酸化の加熱
工程は、同時にイオンで注入された不純物を活性
化、拡散させる効果も有する。次に基体１表面に
清浄なゲート酸化膜１１を形成し、次にこのゲー
ト酸化膜１１表面に多結晶シリコン層１２を形成
し、不必要な部分をエツチングにより除去する。
そして、この残された多結晶シリコン層１２をマ
スクとして酸化シリコン膜のエツチングを行な
い、ソース・ドレイン領域にあたるゲート酸化膜
１１を除去する。その後、選択拡散法あるいは、
イオン注入法により、ＰチヤンネルMOSトラン
ジスタのドレイン、ソース拡散層１３，１３ａと
ＮチヤンネルMOSトランジスタのドレイン、ソ
ース拡散層１４，１４ａとを夫々別々に形成する
（第１図ｅ）。この時、ＰチヤンネルMOSトラン
ジスタのゲート多結晶シリコン層にはＰ型不純物
が導入され、ＮチヤンネルMOSトランジスタの
それにはＮ型不純物が導入される。次にゲート多
結晶シリコン層１２等を絶縁するために基体表面
に酸化シリコン膜１５を形成する。次にコンタク
ト窓を開け、アルミニウムを真空蒸着し、アルミ
配線１６を形成する（第１図ｆ）。この従来の方
法ではＰチヤンネルトランジスタのしきい値電圧
は基体１の不純物濃度で決まり、フイールド酸化
シリコン膜領域のしきい値は、イオン注入により
基体表面の不純物濃度を高くし、しきい値電圧を
上げている。上記の方法で、高速化をはかるため
低濃度の基体を用いると、Ｐチヤンネルトランジ
スタのしきい値は低くなる。これを所望のＰチヤ
ンネルトランジスタのしきい値を得るためにはリ
ンをチヤンネル領域にイオン注入することにより
しきい値を高めることが必要となり、さらに工程
を長くする結果となる。 Next, after removing the photoresist film 8,
Oxidation is performed for several hours at a high temperature of 1000° C. in a steam atmosphere to form a field silicon oxide film 10 having a local oxidation (LOCOS) structure with a thickness of 1.0 μm or more. Next, the oxidation-resistant film 4, which is a mask for the selective oxidation, and the thin silicon oxide film 3 under the film
remove. (FIG. 1d) The selective oxidation heating step described above also has the effect of simultaneously activating and diffusing impurities implanted with ions. Next, a clean gate oxide film 11 is formed on the surface of the substrate 1, and then a polycrystalline silicon layer 12 is formed on the surface of this gate oxide film 11, and unnecessary portions are removed by etching.
Then, using the remaining polycrystalline silicon layer 12 as a mask, the silicon oxide film is etched to remove the gate oxide film 11 corresponding to the source/drain regions. After that, selective diffusion method or
By ion implantation, the drain and source diffusion layers 13 and 13a of the P-channel MOS transistor and the drain and source diffusion layers 14 and 14a of the N-channel MOS transistor are formed separately (FIG. 1e). At this time, P-type impurities are introduced into the gate polycrystalline silicon layer of the P-channel MOS transistor, and N-type impurities are introduced into the gate polycrystalline silicon layer of the N-channel MOS transistor. Next, a silicon oxide film 15 is formed on the surface of the substrate to insulate the gate polycrystalline silicon layer 12 and the like. Next, a contact window is opened and aluminum is vacuum-deposited to form an aluminum wiring 16 (FIG. 1f). In this conventional method, the threshold voltage of the P-channel transistor is determined by the impurity concentration of the substrate 1, and the threshold voltage of the field silicon oxide film region is determined by increasing the impurity concentration on the substrate surface by ion implantation. I'm raising it. In the above method, if a low concentration substrate is used in order to increase the speed, the threshold value of the P channel transistor will be lowered. In order to obtain the desired threshold voltage of the P-channel transistor, it is necessary to increase the threshold voltage by ion-implanting phosphorus into the channel region, which further lengthens the process.
本発明の目的は製造工程が少なく、かつ高速動
作の可能な半導体装置の製造方法を提供すること
にある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that requires fewer manufacturing steps and is capable of high-speed operation.
本発明による半導体装置の製造方法は一導電型
半導体基体表面全面の一部に逆導電型領域（ウエ
ル）を形成したのち、該ウエル領域を除く基体表
面に一導電型不純物をイオン注入する工程と、基
体全面にうすい熱酸化膜を形成し、次に窒化シリ
コン膜を形成後、ソース・ドレイン拡散層及びチ
ヤンネルを形成すべき領域を除く領域の窒化シリ
コン膜を除去した後基体表面を酸化して絶縁分離
領域を形成する工程と、ソース・ドレイン拡散層
及びチヤンネル形成領域の窒化シリコン膜を除去
後ゲート酸化膜を形成し、ゲート電極となるべき
多結晶シリコン層を形成する工程とを含むことを
特徴とする。 The method for manufacturing a semiconductor device according to the present invention includes the steps of forming an opposite conductivity type region (well) on a part of the entire surface of a semiconductor substrate of one conductivity type, and then ion-implanting impurities of one conductivity type into the surface of the substrate excluding the well region. , a thin thermal oxide film is formed on the entire surface of the substrate, then a silicon nitride film is formed, and the silicon nitride film is removed in areas other than areas where source/drain diffusion layers and channels are to be formed, and then the surface of the substrate is oxidized. The process includes the steps of forming an insulating isolation region, and forming a gate oxide film after removing the silicon nitride film in the source/drain diffusion layer and channel formation region, and forming a polycrystalline silicon layer to become the gate electrode. Features.
本発明によれば５×1014cm-3程度の低濃度基板
上に、Ｐウエルを形成し、更にＰウエル領域を除
く領域にＮ型不純物を1011〜1012cm-2のドーズ量
でイオン注入を行なつた後にLOCOS構造を形成
するための窒化シリコン膜の形成、選択エツチを
行ない選択酸化によるLOCOS構造を形成する相
補型MOSトランジスタで多結晶シリコンゲート
電極を有する半導体装置の製造方法が得られる。 According to the present invention, a P-well is formed on a low-concentration substrate of about 5×10 14 cm -3 and an N-type impurity is added to the region excluding the P-well region at a dose of 10 11 to 10 12 cm -2. A method for manufacturing a semiconductor device having a polycrystalline silicon gate electrode with a complementary MOS transistor in which a silicon nitride film is formed to form a LOCOS structure after ion implantation, selective etching is performed, and a LOCOS structure is formed by selective oxidation. can get.
以下、本発明の実施例について第２図ａ〜ｆを
参照して詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2a to 2f.
Ｎ型基体１７表面の一部にＰ型のウエル領域１
８を形成したのち、薄い酸化シリコン膜１９を形
成し、Ｎチヤンネルトランジスタを形成する領域
の基体表面にフオトレジスト２０をマスクとして
Ｐ型ウエル１８の形成されていない表面領域２１
全面にリン等のＮ型不純物を1011〜２×1012cm-2
のドーズ量でイオン注入する。（第２図ａ）次に
リンのイオン注入後、フオトレジスト２０及び酸
化シリコン膜１９を除去し、新たに基体１７の表
面にうすい酸化シリコン膜２２を形成し、更にそ
の膜２２の上に同じ厚さの窒化シリコン膜２３を
形成する（第２図ｂ）。続いてフイールド酸化シ
リコン膜を形成する領域の上記窒化シリコン膜２
３及び、この膜下の酸化シリコン膜２２をフオト
レジスト膜２４をマスクにして除去する。次に、
Ｐチヤンネルトランジスタを形成する領域の基体
１７上をフオトレジスト２５でおおい、Ｎチヤン
ネルトランジスタのフイールド領域の基体表面に
ボロン等のＰ型不純物２６をイオン注入する（第
２図ｃ）。次に上記のフオトレジスト膜２４，２
５を除去したのち、水蒸気雰囲気中で高温酸化
し、局部酸化構造のフイールド酸化膜２７を1.0μ
ｍ以上形成する。次に、素子活性領域に残した難
酸化性被膜２３および酸化シリコン膜２２をエツ
チング除去する（第２図ｄ）。続いて基体１７表
面に清浄なゲート酸化膜２８を形成し、次にこの
ゲート酸化膜２８上に多結晶シリコン層２９を形
成し、フオトエツチングにより不要な部分を除去
する。その後、フオトレジストをマスクとするイ
オン注入法あるいは酸化シリコン膜又は、窒化シ
リコン膜をマスクとする選択拡散法によりＰチヤ
ンネル素子、Ｎチヤンネル素子のソース拡散層３
０，３１、ドレイン拡散層３０ａ，３１ａを形成
する（第２図ｅ）。なお、この時、Ｐチヤンネル
素子のゲートにはＰ型不純物が、Ｎチヤンネル素
子のゲートにはＮ型不純物が導入される。次にゲ
ート電極の多結晶シリコン２９と拡散層を表面保
護するため、基板上面に熱酸化もしくは気相成長
法による酸化シリコン膜３２を形成する。次にコ
ンタクト窓を開け、アルミニウムを真空蒸着し、
フオトエツチングによりアルミ配線３３を形成す
る（第２図ｆ）。 A P-type well region 1 is formed on a part of the surface of the N-type substrate 17.
8, a thin silicon oxide film 19 is formed on the substrate surface in the region where the N-channel transistor is to be formed, and a surface region 21 where the P-type well 18 is not formed is formed using the photoresist 20 as a mask.
Add N-type impurities such as phosphorus to the entire surface at 10 11 to 2×10 12 cm -2
Ion implantation is performed at a dose of . (Fig. 2a) Next, after phosphorus ion implantation, the photoresist 20 and the silicon oxide film 19 are removed, a thin silicon oxide film 22 is newly formed on the surface of the base 17, and the same A thick silicon nitride film 23 is formed (FIG. 2b). Next, the silicon nitride film 2 in the region where the field silicon oxide film is to be formed is
3, and the silicon oxide film 22 underneath this film is removed using the photoresist film 24 as a mask. next,
The substrate 17 in the region where the P-channel transistor is to be formed is covered with a photoresist 25, and a P-type impurity 26 such as boron is ion-implanted into the surface of the substrate in the field region of the N-channel transistor (FIG. 2c). Next, the above photoresist films 24, 2
After removing 5, it is oxidized at high temperature in a steam atmosphere to form a field oxide film 27 with a local oxidation structure of 1.0 μm.
m or more. Next, the oxidation-resistant film 23 and silicon oxide film 22 left in the element active region are removed by etching (FIG. 2d). Subsequently, a clean gate oxide film 28 is formed on the surface of the substrate 17, and then a polycrystalline silicon layer 29 is formed on this gate oxide film 28, and unnecessary portions are removed by photoetching. Thereafter, the source diffusion layer 3 of the P channel element and the N channel element is formed by ion implantation using a photoresist as a mask or selective diffusion using a silicon oxide film or silicon nitride film as a mask.
0 and 31, and drain diffusion layers 30a and 31a are formed (FIG. 2e). Note that at this time, a P-type impurity is introduced into the gate of the P-channel element, and an N-type impurity is introduced into the gate of the N-channel element. Next, in order to protect the surface of the polycrystalline silicon 29 of the gate electrode and the diffusion layer, a silicon oxide film 32 is formed on the upper surface of the substrate by thermal oxidation or vapor phase growth. Next, open the contact window and vacuum-deposit aluminum.
Aluminum wiring 33 is formed by photoetching (FIG. 2f).
上述したような本発明にかかるCMOS半導体
装置では低濃度の基体を用いるために生ずるＰチ
ヤンネルトランジスタのしきい値の低下とフイー
ルド酸化膜領域の寄生MOSトランジスタのしき
い値の低下を防ぎ、低濃度基体を用いているため
拡散層の底面部の接合容量が減少する。同時にＮ
型低濃度の基体を用いるため、同じ拡散深さでも
不純物濃度の低いＰウエル領域を形成できるため
Ｎチヤンネルトランジスタの接合容量も少なくで
き、高速化に適した集積回路装置が実現できる。
また本発明はＰ型基体を用いた場合にも適用でき
る。 In the CMOS semiconductor device according to the present invention as described above, the lowering of the threshold voltage of the P channel transistor and the lowering of the threshold voltage of the parasitic MOS transistor in the field oxide film region, which occur due to the use of a low-concentration substrate, can be prevented. Since a base is used, the junction capacitance at the bottom of the diffusion layer is reduced. At the same time N
Since a low-concentration substrate is used, a P-well region with a low impurity concentration can be formed at the same diffusion depth, so the junction capacitance of an N-channel transistor can be reduced, and an integrated circuit device suitable for high speed operation can be realized.
Further, the present invention can also be applied when a P-type substrate is used.
第１図ａ〜ｆは従来の半導体装置の製造方法を
順次工程順に示す断面図である。第２図ａ〜ｆは
本発明の一実施例による半導体装置の製造方法を
工程順に示す断面図である。
１，１７……Ｎ型基体、２，１８……Ｐ型ウエ
ル、３，１９，２２……酸化シリコン膜、４，２
３……難酸化性被膜、５，６，８，２０，２４，
２５……フオトレジスト膜、７，２６……アクセ
プタ不純物、９，２１……ドナー不純物、７ａ，
２６ａ……P+拡散層、９ａ……N+拡散層、２１
ａ……低濃度Ｎ型拡散層、１０，２７……フイー
ルド酸化シリコン膜、１１，２８……ゲート酸化
シリコン膜、１２，２９……多結晶シリコン層、
１３，１３ａ，３０，３０ａ……N+拡散層、１
４，１４ａ，３１，３１ａ……P+拡散層、１５，
３２……酸化シリコン膜、１６，３３……Al電
極。
FIGS. 1a to 1f are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. FIGS. 2a to 2f are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of steps. 1,17...N-type substrate, 2,18...P-type well, 3,19,22...Silicon oxide film, 4,2
3... Oxidation-resistant coating, 5, 6, 8, 20, 24,
25... Photoresist film, 7, 26... Acceptor impurity, 9, 21... Donor impurity, 7a,
26a...P + diffusion layer, 9a...N + diffusion layer, 21
a... Low concentration N-type diffusion layer, 10, 27... Field silicon oxide film, 11, 28... Gate silicon oxide film, 12, 29... Polycrystalline silicon layer,
13, 13a, 30, 30a...N + diffusion layer, 1
4, 14a, 31, 31a...P + diffusion layer, 15,
32...Silicon oxide film, 16, 33...Al electrode.
Claims (1)
逆導電型のウエル領域を形成する工程と、しかる
後前記ウエル領域をマスクで覆い前記基体表面に
前記一導電型の不純物を導入し、チヤンネルスト
ツパー領域の形成とチヤンネルドープとを同時に
行なう工程と、しかる後前記基板および前記ウエ
ル領域の素子形成予定領域にゲート酸化膜および
窒化膜を形成する工程と、続いて前記ウエル領域
のうち前記ゲート酸化膜が形成されていない領域
にのみ逆導電型のチヤンネルストツパー領域を形
成する工程と、その後素子形成予定領域以外の領
域を選択酸化する工程と、しかる後前記基体およ
び前記ウエル領域に夫々素子を形成する工程とを
含むことを特徴とする半導体装置の製造方法。1. A step of forming a well region of an opposite conductivity type on a part of the surface of a low concentration semiconductor substrate of one conductivity type, and then covering the well region with a mask and introducing an impurity of the one conductivity type into the surface of the substrate, A step of forming a channel stopper region and channel doping at the same time, a step of forming a gate oxide film and a nitride film on the substrate and the region of the well region where the device is to be formed, and then a step of forming the channel stopper region in the well region. A step of forming a channel stopper region of the opposite conductivity type only in the region where the gate oxide film is not formed, a step of selectively oxidizing the region other than the region where the element is to be formed, and then a step of selectively oxidizing the region other than the region where the device is to be formed, and then forming the channel stopper region on the substrate and the well region, respectively. 1. A method for manufacturing a semiconductor device, comprising the step of forming an element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15254478A JPS5578541A (en) | 1978-12-08 | 1978-12-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15254478A JPS5578541A (en) | 1978-12-08 | 1978-12-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5578541A JPS5578541A (en) | 1980-06-13 |
| JPS6348179B2 true JPS6348179B2 (en) | 1988-09-28 |
Family
ID=15542771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15254478A Granted JPS5578541A (en) | 1978-12-08 | 1978-12-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5578541A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59161838A (en) * | 1983-03-07 | 1984-09-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS59161859A (en) * | 1983-03-07 | 1984-09-12 | Toshiba Corp | Complementary type metal oxide semiconductor device and manufacture thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5292489A (en) * | 1976-01-30 | 1977-08-03 | Hitachi Ltd | Manufacture of c-mis semiconductor |
-
1978
- 1978-12-08 JP JP15254478A patent/JPS5578541A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5292489A (en) * | 1976-01-30 | 1977-08-03 | Hitachi Ltd | Manufacture of c-mis semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5578541A (en) | 1980-06-13 |
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