JPS59161838A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the generation of N-P junction leakage current to occur at the side surfaces of an isolating region by a method wherein when the buried element isolating region is provided in a semiconductor device, a P type inversion preventing layer is provided on the undersurface of an N type diffusion layer to come in contact to the region. CONSTITUTION:A groove is bored in the surface layer on a P type Si substrate 1 and in the groove is buried a separating material 12 for using the groove as an element isolating region 13. Interposing the region 13 between, an N channel MOS transistor is formed on one side and a P channel MOS transistor is formed on the other side. Namely, on the N channel element side are formed by diffusion a source region 171 and a drain region 181, both of which are a shallow N<+> type one, and a gate electrode 161 is attached to these regions through a gate insulating film 151 formed between the regions 171 and 181. In this constitution, a P<-> type conversion preventing region 10 is provided under the undersurface of the region 181, which comes in contact to the region 13. Though the resion 171 side is not illustrated in the diagram, a conversion preventing region is formed on the region side as well. On the other hand, on the P channel element side is formed an N type well region 14, and a source region 172 and a drain region 182, both of which are a P<+> type one, are provided here as well. However, the inversion preventing region becomes unnecessary here by specifying the concentration of the well region 14.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device and a method for manufacturing the same.

In particular, the present invention relates to a semiconductor device with improved element isolation technology and a method for manufacturing the same.

[Technical background of the invention and its problems]

In a semiconductor device, an element isolation region is provided to electrically isolate a large number of elements formed on the surface of a semiconductor substrate. As a technique for forming such an element isolation region,
Conventionally, the pLOCO8 method has been widely used. However, in this method, a silicon oxide film (element isolation region) is formed by selectively oxidizing the semiconductor substrate using an oxidation-resistant film such as a silicon nitride film or a silicon film.
White lily caused by bird's peak or nitride film? This causes problems such as

For this reason, recently, grooves have been created in semiconductor substrates,
A method has been developed for forming a buried element isolation region by embedding an isolation material made of an insulating material or the like in this groove. Since the element isolation region formed by this method is embedded in the semiconductor substrate, it has advantages such as a flat substrate surface and resistance to minute wiring breaks. However, if an impurity diffusion layer used as a source or drain, in particular an n-type diffusion layer, is formed on the surface of a semiconductor substrate in contact with the side surface of the buried element isolation region, the insulating material constituting the element isolation region becomes Since the interface between the separation material and the substrate is leaky, there is a drawback that n+-p junction leakage current occurs, degrading device characteristics.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to provide a semiconductor device and a method for manufacturing the same, which have good device characteristics and prevent n-p junction leakage current from occurring on the side surfaces of a buried device isolation region in contact with an n-type diffusion layer.

[Summary of the invention]

The main objective of the present invention is to prevent the occurrence of n-p junction leakage current on the side surface of the buried type device isolation region by providing a p-type anti-inversion layer on the side surface of the buried device isolation region in contact with the n-type diffusion layer. do.

That is, the first invention of the present application includes a semiconductor substrate, a buried element isolation region provided in the semiconductor substrate and comprising a groove formed in the substrate and an isolation material embedded in the groove, and a surface of the semiconductor substrate. an n-type diffusion layer provided in a part of the semiconductor substrate in contact with the side surface of the element isolation region, and a p-type inversion prevention layer provided in the semiconductor substrate portion on the side surface of the element isolation region in contact with the n-type diffusion layer. It is characterized by the following:

As the semiconductor substrate, for example, a p-type semiconductor substrate, a p-
Examples include an n-type semiconductor substrate having a well region or a p-type semiconductor layer provided on an insulating substrate.

The n-type diffusion layer is used as a source, a drain, or a diffusion wiring.

Further, a second invention of the present application includes a step of forming a first film having an opening wider than a width of a groove to be formed on a semiconductor substrate, and a portion of the semiconductor substrate located near one inner wall of the opening. doping with p-type impurities to form a p-type diffusion layer; forming a second film around at least the opening of the first film; Inside the opening of the first coating II by etching
a step of leaving a second coating on the wall; etching a portion of the semiconductor substrate where most of the p-type diffusion layer is formed using the first coating and the remaining second coating as a mask to form a groove; A step of leaving a p-type diffusion layer on one side surface, and forming a buried element isolation region by burying an isolation material in the trench, and then forming an n-type diffusion layer on the surface of the semiconductor substrate with the remaining p-type diffusion. The method is characterized by comprising a step of selectively forming the layer so as to be in contact with the side surface of the buried element isolation region provided with the layer.

As the material of the first coating, for example, 5i02+S j
Various metals such as 3N4, AL, At alloy 2MO, etc. can be used.

The second coating needs to be formed from a material that has selective etching properties with respect to the first coating, and 5i3N4 is used as the material for the second coating. The first coating is S io 2
In this case, a metal such as U or Kt gold alloy is used as the material of the second coating.

The means for embedding the isolation material into the trench includes, for example, a method of depositing an insulating film with a thickness equal to or larger than the width of the trench, etching back the insulating film, and embedding an isolation material made of an insulating material; After forming a thin oxide film or nitride film on the inner peripheral surface of the groove,
A method of depositing an insulating film with a thickness equal to or greater than the width of the trench, etching back the insulating film, and embedding an isolation material made of an insulating material may be adopted. However, in the latter method, a polycrystalline silicon film or an amorphous silicon film can be used instead of the insulating film.

Note that after the groove is formed, a carrier killer layer may be formed by ion-implanting impurities such as oxygen, carbon, gold, etc. into the semiconductor substrate at the bottom of the groove using the first film and the remaining second film as masks.

[Embodiments of the invention]

Next, we will introduce the present invention into a complementary type MO8) U/Sosta (CMO8)
An example in which this method is applied will be described along with a manufacturing method.

(1) First, after growing a thermal oxide film 2 with a thickness of, for example, 500× on the main surface of a p-type silicon substrate 1 by a thermal oxidation method,
A 5i3N4 film 3 having a thickness of 4000× was deposited as a first film on the entire surface. By using photoetching technology,
i Opening 41r wider than the width of the groove to be formed by selectively removing the 5t3N4 film 3: formed (as shown in Figure 1)
.

(11) Next, a resist/arm turn 5 is formed by photolithography so that the vicinity of one inner side wall of the opening 4 is exposed, and then a p-type impurity is added using the Si3N4 film 3 and the resist/arm turn as a mask. , for example, by implanting ions into the substrate 1 through the thermal oxide film 2 exposing boron? A ion-implanted layer 6 was formed (as shown in FIG. 2). Subsequently, a 7f XO8102 film having a thickness of 3000, for example, was deposited on the entire surface by CVD, and then heat treated. At this time, as shown in FIG. 3, the boron ion implanted layer is activated and diffused so that one end is
．． A p-type diffusion layer 8 extending below the N4 film 3 was formed.

(iii) Next, the 9SiO□ film 7 is removed to the extent of its thickness by reactive ion etching (RIE), and an SIO2 film 7 is formed on the inner wall of the opening 4 of the SiN film 3.
4' remained (as shown in Figure 4). In addition, in this process,
Thermal oxide film 2 serves as a buffer for RIE. Next, using the 513N4 film 3 and the remaining 5XO2 film 7' as a mask, the exposed thermal oxide film 2 was removed by etching.
Furthermore, silicon substrate 1 was selectively removed to a predetermined depth using RIg. At this time, a portion of the silicon substrate 1 on which most of the p-type diffusion layer 8 is formed is removed to form a groove 9, and a type 1 diffusion layer remains in a portion of the substrate 1 on one side of the groove 9. As a result, 1) a p-type anti-inversion layer 10 was formed (as shown in FIG. 5).

lIψ Then, Si3N4 film 3, remaining 5io2v'E
After removing the thermal oxide film 2, a 5IO2 film 11 with a thickness equal to or more than the width of the trench 9 is deposited on the entire surface, and the inside of the trench 9 is filled with S.
It was fully embedded with iO□ (as shown in Figure 6). Continuing,
The 8102 film 11 was etched back. As a result, the isolation material 12 having a size of 5 inches was embedded in the trench 9', and a buried element isolation region 13 was formed.

Subsequently, an n-type impurity such as arsenic was selectively ion-implanted into the p-type silicon substrate 1 and diffused to form an n-well region 14 (as shown in FIG. 7).

(V) Next, a dirt oxide film 151 is formed on the p-type silicon substrate 1 and the n-well region 14 separated by the buried element isolation region 13 according to a conventional method.

A dirt electrode 161p16□ made of, for example, polycrystalline silicon was formed through the 15□. Subsequently, a Renost pattern (not shown) covering the n-well region side is formed,
This Lennost pattern, the buried element isolation region 13, and the dirt electrode 161 were used as a -substrate, and n-type impurities, such as arsenic, were ion-implanted into the p-type silicon substrate 1. Continuing, the Lenost pattern is removed and the silicon substrate 1 is placed again.
After forming a Lennost 9 turn (not shown) covering an island-like region, a p-type impurity such as zolon is added to the n-well region using the Lenost pattern, the buried element isolation region 13 and the gate electrode 162 as one mask. Ion implantation into 14 and 7
Ta. Thereafter, the Rennost pattern is removed and heat treatment is performed to form a p-type anti-inversion layer 10 on the surface of the silicon substrate 1.
Square-shaped source/drain regions 171 and 181 were formed, respectively, with one end in contact with the side surface of the buried element isolation region 13 provided with. At the same time, f-type source/drain regions 172.18□ were formed in the n-well region 14, and 0MO8 was manufactured (as shown in FIG. 8).

As shown in FIG. 8, the OMO8 of the present invention has a trench 9 in a p-type silicon substrate 1 and a buried element isolation region 13 made of an isolation material 12 buried in the trench 9. A layer type source/drain region 17. of an n-channel MOS transistor is formed in the island region 17.1. ,18.
is provided in contact with the side surface of the element isolation region 13, and a p-type inversion prevention layer 10 (the source region side is not shown) is provided on the side surface of the element isolation region 13 in contact with the meter-shaped source and drain regions 171 and 181. The structure has been established. Therefore, when the groove 9 of the buried element isolation region 13 is formed, the p-type silicon substrate l around it becomes leaky, and as a result, the side-shaped source, drain/region 171
.

It is possible to prevent junction current leak between 181 and group 1, and to obtain CIviO8fr: with excellent device characteristics.

Furthermore, if the concentration of the well region 14 is set to about 2×1016Δm3 or more, the p+ type source and drain regions 1721
8□ and the n-well region 14, the p-type source and drain regions 172
．． 1g, on the side surface of the buried element isolation region 13 in contact with
It is not necessary to form an n-type anti-inversion layer in the well region 14.

Further, according to the method of the present invention, Si3N4 having the opening 4
1c with membrane 3 as part of the mask? A p-type diffusion layer 8 is formed by implanting ions such as ions into a p-type silicon substrate 1 and diffusing them to form a p-type diffusion layer 8 extending to a portion of the substrate 1 under the 5IN4 film 3.
Furthermore, a 5iO7 film 71 is placed on the peripheral side of the lower part 4 between the Si6N4 films 30.
remain, Si3N4 film 3 and remaining SiO□ film 7/1
By etching the substrate 1 as a mask, it is possible to form a trench 9 which is a part of the buried element isolation region, and also to form an F-type inversion prevention layer 10 using the p-type diffusion layer remaining on the side surface of the trench 9. . Therefore, the nine-layer type source and drain regions 174 can be formed by an extremely simple process.
A highly reliable 0MO8 in which n-p junction current leakage at 181 is prevented can be manufactured.

Note that the present invention is not limited to 0MO8 as in the above embodiments, but is applicable to n-channel MO8) Lannostar, n-channel M08)
It can be similarly applied to NOS, n-channel MAO8, etc. Further, in the above embodiment, the case where the n-type diffusion layer is applied to the n-type source and drain regions of the n-channel MO8 transistor has been described, but it may be used for the n-type diffusion wiring.

〔Effect of the invention〕

As detailed above, according to the present invention, a semiconductor device having good device characteristics that prevents the occurrence of n-p junction leakage current on the side surface of the buried device isolation region in contact with the n-type diffusion layer;
The present invention also provides a method for easily manufacturing such a semiconductor device.

[Brief explanation of drawings]

FIGS. 1 to 8 are cross-sectional views showing the manufacturing process of 0MO8 in an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type silicon substrate, 3...S i 3N4 film, 4...opening, 7'...residual SiO□ film, 9...
・Groove portion, 10...p-type inversion prevention layer, 12...5I
Isolation material made of O2, 13... Buried element isolation region, 14... N-well region, 161, 162... Dirt electrode, 171... n+W'J-space region, 181
. . . meter type drain region, 172 . . . type source region, 182 . . . p + type drain region. Applicant's agent Patent attorney Takehiko Suzue
Ward n (0 bin
Ren (-, 00 Castle Castle

Claims (9)

[Claims] (1) A semiconductor substrate, provided on this semiconductor substrate,
a buried type element isolation region made of a groove formed in the base and an isolation material embedded in the groove; and an n-type element isolation region provided on a part of the surface of the semiconductor base so as to be in contact with a side surface of the element isolation region. A semiconductor device comprising: a diffusion layer; and a p-type inversion prevention layer provided on a semiconductor substrate portion on a side surface of the element isolation region in contact with the n-type diffusion layer. (2) If the semiconductor substrate is an n-type semiconductor substrate having a p-well region, a buried element isolation region is provided near the interface in the depth direction between the well region and the substrate, and a source or a source is provided in the well region. An n-type diffusion layer serving as a drain is provided in contact with a side surface of the element isolation region, and a p-type inversion prevention layer is provided in a p-well region on the side surface of the element isolation region in contact with the n-type diffusion layer. A semiconductor device according to claim 1. (3) Forming a first film having an opening wider than the width of the groove to be formed on the semiconductor substrate, and doping the semiconductor substrate portion of the opening with an impurity that imparts p-type to diffuse p-type. forming a second layer at least around the first layer including the opening, and anisotropically etching the second layer. a step of leaving a second coating on the wall;
Using the first coating and the remaining second coating as a mask, the semiconductor substrate portion where most of the p-type diffusion layer is formed is etched to form a groove, and a p-type diffusion layer is formed on one side of the groove. After forming a buried type element isolation region by burying an isolation material in the trench, an n-type diffusion layer is formed on the surface of the semiconductor substrate, and a buried type element isolation process is performed in which an n-type diffusion layer is provided on the surface of the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising a step of selectively forming the region so as to be in contact with a side surface of the region. (4) The method for manufacturing a semiconductor device according to claim 3, wherein the first film is made of silicon dioxide, metal, or silicon nitride. (5) The method of manufacturing a semiconductor device according to claim 3, wherein the second film is made of a material that has selective etching properties with respect to the first film. (6) The method for manufacturing a semiconductor device according to claim 3, characterized in that Gyron is used as the p-type impurity. (7) After the groove is formed, the semiconductor substrate at the bottom of the groove is doped with impurities using the first film and the remaining second film as masks to form a carrier killer layer. A method for manufacturing a semiconductor device. (8) The method for manufacturing a semiconductor device according to claim 7, characterized in that oxygen, carbon, or gold is used as an impurity. (9) The method for manufacturing a semiconductor device according to claim 3, wherein the p-type diffusion layer is in contact with the element isolation layer and is used as an inversion prevention layer.