JPH04132240A - Semiconductor device production method - Google Patents

Abstract

PURPOSE:To form an oxide film for device separation having no level difference at the interface with an active element region by using a resist pattern in the shape of the active element region as the mask for anistropic etching. CONSTITUTION:Anistropic etching is used to form a channel 1a on the surface of a silicon substrate 1 to a specified depth in the perpendicular direction to the substrate surface with the resist pattern 2 in the shape of the active element region as a mask. After that, same conductivity ion impurities are implanted in the channel 1a section of the silicon substrate 1 and the devices are separated with an electric liquid. A channel stop region 3 is formed to ensure that the device separation region does not function as a parasitic MOS transistor. Next, an H2SiF6 solution 5 with an excessive amount of SiO2 dissolved is placed in a container 4, the silicon substrate 1 is put in this solution with the resist pattern 2 attached, and when H2BO3 is added to the H2SiF6 solution 5, the SiO2 from the H2SiF6 solution 5 with an excessive amount of SiO2 dissolved begins growing inside of the channel 1a. The SiO2 film 6 is formed until the inside of the channel 1a is completely filled and device separation achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device 1, for example, MO3
This is suitable for application to LSI manufacturing.

[Conventional technology]

As an element isolation method for MO3 type semiconductor devices, L
The OCO3 method is most commonly used.

When performing element isolation using this LOCO3 method, the second
As shown in Figure A, first, a thin silicon dioxide film (pad oxidation film 1
After forming 02, C is deposited on this silicon dioxide film 102.
Silicon nitride M103 is formed by the VD method. Thereafter, a resist pattern 104 having a shape corresponding to the active element region is formed on the silicon nitride substrate 101.

Next, impurity ions for forming a channel stop region are ion-implanted into the silicon substrate 101 using this resist pattern 104 as a mask.

Next, as shown in FIG. 2B, this resist pattern 1
04 as a mask, the silicon nitride film 103 is etched.

Next, after removing this resist pattern 104, the silicon substrate 101 is thermally oxidized using the patterned silicon nitride film 103 as an oxidation mask. As a result, as shown in FIG. 2C, a field oxide film 105 is formed and element isolation is performed. At the same time, a channel stop region 106 is formed under this field oxide film 105 by the previously ion-implanted impurities for forming a channel stop region.

Next, silicon nitride film 103 and silicon dioxide film 10
2 is removed by etching.

After this, as shown in the second diagram, the field oxide film 10
A gate oxide film 107 is formed on the surface of the active element region surrounded by 5 by thermal oxidation.

[Problem to be solved by the invention]

As described above, in the conventional semiconductor device manufacturing method in which element isolation is performed using the LOCO3 method, a large step exists between the field oxide film 105 and the active element region.

For this reason, it became difficult to pattern the conductor film for forming the wiring later, and the wiring was easily broken. In addition, since the thickness of the gate oxide film 107 at the boundary with the field oxide film 105 increases (bird's beak), there is a problem in that the effective dimensions of the active element region become smaller.

Furthermore, there is also the problem that the threshold voltage of the MOS transistor becomes high due to the narrow channel effect.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which an oxide film for element isolation can be formed without forming a step at the boundary with an active element region.

Another object of the present invention is to prevent the thickness of the gate oxide film formed on the surface of the active element region from increasing at the boundary with the field oxide film, and to make the active element area have dimensions as designed. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform the following steps.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent narrow channel effects.

(Means for Solving the Problems) In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a resist pattern having a shape corresponding to an active element region on a semiconductor substrate; A process of forming grooves for element isolation by anisotropically etching the semiconductor substrate using a mask as a mask, and forming SiO into the grooves using precipitation of SiO□ from the liquid phase.
□Process of forming a film.

In one embodiment of the present invention, after forming the trench, impurity ions are implanted to form a channel stop region.

LPD (Liq
uid Phase Deposition) method can be used. In this method, immediately before immersing the substrate in a HzSiF solution in which Sin is supersaturated, HJ
In this method, by adding Oz, Sin is precipitated only in areas where no photoresist is present on the semiconductor substrate.

[Effect]

According to the method for manufacturing a semiconductor device of the present invention configured as described above, a 5in2 film can be formed only within the groove of the semiconductor substrate, and no SiO□ film will grow on the resist pattern. Then, the Si formed in the groove in this way
Element isolation is performed by the O□ film.

In this case, by completely filling the inside of the trench with the SiO□ film, this SiO□ film, that is, the oxide film for element isolation, can be formed so that no step is formed at the boundary with the active element region. This prevents difficulty in patterning a conductive film for forming interconnects or breaks in interconnects when forming interconnects.

In addition, unlike when element isolation is performed using the LOCO3 method, the thickness of the gate oxide film at the boundary with the element isolation oxide film does not increase, so the active element area can be made to the designed dimensions. can.

Furthermore, narrow channel effects can also be prevented.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to the drawings.

1A to 1E are MOSLs according to an embodiment of the present invention.
A method for manufacturing SI will be shown.

In this embodiment, as shown in FIG. 1A, first,
A resist pattern 2 having a shape corresponding to an active element region is formed on a p-type or n-type silicon substrate 1 by lithography.

Next, using resist pattern 2 as a mask, silicon substrate 1 is anisotropically etched to a predetermined depth in a direction perpendicular to the substrate surface, for example, by reactive ion etching (RIE). As a result, a trench 1a is formed in the element isolation region, as shown in FIG. 1B. Specifically, the depth of this groove 1a is, for example, about 3000 to 1000 people.

Thereafter, impurities of the same conductivity type as the silicon substrate 1 are ion-implanted into the silicon substrate 1 in the groove 1a to electrically isolate the elements, and the element isolation region becomes a parasitic MO3) transistor. A channel stop region 3 is formed to prevent operation. The ion implantation for forming this channel stop region 3 is n
In the case of a channel MOS transistor, an n-type impurity such as boron is added, for example, from 1×10′2 to 3×10
In the case of a p-channel MO3) transistor, ions are implanted at a dose of approximately
Type impurities are ion-implanted at a dose of, for example, about 1xioI2 to 3XIO''/aj.

Next, as shown in FIG. 1C, for example, Si is placed in the container 4.
Add H, SiF, and solution 5 in which O□ is supersaturated, and soak the silicon substrate 1 with the resist pattern 2 formed in this H1SiFi solution 5.
Then, from H2SIF & solution 5 in which Sin is supersaturated, Sin starts to grow inside the groove 1a of the silicon substrate 1. In this case, SiO□ is formed on the resist pattern 2. does not grow.

In this way, as shown in the first diagram, the SiO□ film 6 is formed until the groove la is completely filled. Element isolation is performed by this Sin film 6.

Next, after taking out the silicon substrate 1 from the container 4, the resist pattern 2 is removed. After this, the surface of the silicon substrate 1 is cleaned.

Next, as shown in FIG. 1E, a gate oxide film 7, such as a silicon dioxide film, is formed on the surface of the active element region by thermal oxidation. Next, a polycrystalline silicon film is formed on the entire surface by, for example, a CVD method, and this polycrystalline silicon film is doped with impurities by, for example, a thermal diffusion method or an ion implantation method to lower the resistance, and then this polycrystalline silicon film is etched. is patterned into a predetermined shape. As a result, gate electrode 8 is formed.

Note that this gate electrode 8 can also be formed of, for example, a polycide film (a composite film in which a high melting point metal silicide film is layered on a polycrystalline silicon film doped with impurities); After forming a high melting point metal silicide film on the polycrystalline silicon film, the gate electrode 8 is formed by patterning the high melting point metal silicide film and the polycrystalline silicon film.

Next, this gate electrode 8 and a 5iOz film 6 for element isolation are
By ion-implanting impurities for forming source and drain regions into the silicon substrate l at a high concentration using as a mask, the source region 9 and the drain region IO are formed in a self-aligned manner with respect to the gate electrode 8. MO by these gate electrode 8, source region 9 and drain slope lO
S) A transistor is formed. For example, when an n-type impurity such as arsenic or phosphorus is used as an impurity for forming a source region and a drain region, an n-type source region 9 and drain region 10 are formed. An n-channel MOS transistor is formed. In addition, when an n-type impurity such as boron is used as an impurity for forming the source region and drain region, the source region 9 and drain region 1 of P° type are used.
A p-channel MO3) transistor is formed.

Thereafter, a glabellar insulating film is formed, a contact hole is formed in the glabellar insulating film, a metal wiring is formed, a passivation film is formed, and the desired MOSLSI is completed.

As described above, according to this embodiment, by the LPD method,
Since the SiO□ film 6 for element isolation is formed so as to completely fill the inside of the groove la, this SiO□ film 6 for element isolation
No step occurs at the boundary between the active element region and the active element region. This eliminates the problem of difficulty in patterning a conductive film such as an aluminum film for forming a wiring, or of disconnection of the wiring when forming the wiring.

Also, unlike the case where element isolation is performed by the LOCO3 method, the gate oxidation W at the boundary with the element isolation film 6 is
Since the film thickness of I7 does not increase, the active element Nk
A can be dimensioned as designed. Furthermore, since the narrow channel effect can be prevented, the problem of high threshold voltage of the MOS transistor due to the narrow channel effect is also eliminated.

Although the present invention has been specifically described above with reference to one embodiment, the present invention is not limited to the above-mentioned embodiment, and the above-mentioned embodiment is not limited to various effective modifications based on the technical idea of the present invention. is possible.

For example, in the embodiments described above, the present invention is applied to MO3LS.
Although the present invention has been described for the case where it is applied to the manufacture of I, the present invention can be applied to the manufacture of various semiconductor devices such as bipolar CMOS L-Si and others.

〔Effect of the invention〕

Since the present invention is configured as described above, it is possible to form an oxide film for element isolation so that there is no step difference at the boundary with the active element region, and the active element region can be formed with the dimensions as designed. Furthermore, narrow channel effects can be prevented.

[Brief explanation of the drawing]

FIG. 1A to FIG. 1E are MO3Ls according to an embodiment of the present invention.
Cross-sectional views showing the SI manufacturing method in the order of steps, Figures 2A to 2
The figure is a cross-sectional view showing a conventional MO3 type semiconductor device element isolation method in the order of steps. In addition, in the symbols used in the drawings, l --- Silicon substrate 2 --- Resist pattern 3 ---
-・Channel stop area 6------ Si0g
Film 7 --- Gate oxide film 8 , Gate electrode 9-1 ---. source region drain region

Claims (2)

[Claims] (1) A step of forming a resist pattern with a shape corresponding to an active element region on a semiconductor substrate, and a step of forming trenches for element isolation by anisotropically etching the semiconductor substrate using the resist pattern as a mask. Then, using the precipitation of SiO_2 from the liquid phase, Si is deposited in the groove.
A method for manufacturing a semiconductor device, comprising a step of forming an O_2 film. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of ion-implanting impurities for forming a channel stop region after forming the groove.