KR100335800B1 - CMOS transistor and method for manufacturing the same - Google Patents

Abstract

The present invention forms a contact that is an electrical connection path between a channel region and a semiconductor substrate, and then grows an epitaxial layer for forming a channel region, thereby preventing the semiconductor substrate from floating. Oxide Semi Conductor (CMOS) transistors and a method of manufacturing the same.

In the CMOS transistor of the present invention and a method of manufacturing the same, an epitaxial layer for forming a channel region is grown after forming a contact, which is an electrical connection passage between a channel region and a semiconductor substrate, thereby preventing the semiconductor substrate from floating, thereby stabilizing a threshold voltage. Since it prevents the occurrence of a kink phenomenon, there is a feature to improve the characteristics and reliability of the device.

Description

CMOS transistor and method for manufacturing the same {CMOS transistor and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS metal transistor (CMOS) transistor and a method for fabricating the same. Particularly, an epitaxial layer for forming a channel region is formed after a contact is formed between the channel region and a semiconductor substrate. The present invention relates to a CMOS transistor and a method for manufacturing the same, which grow layers to improve electrical characteristics of the device.

In the method of manufacturing a CMOS transistor according to the prior art, as shown in FIG. 1A, n-type impurity ions are implanted into a surface of a semiconductor substrate 11 to form a drain region 12.

As shown in FIG. 1B, a first PSG layer 13, an oxide film 14, a nitride film 15, and a second PSG are formed on a semiconductor substrate 11 on which the drain region 12 is formed. Layers 16 are formed sequentially.

As shown in FIG. 1C, after the photoresist layer 17 is coated on the second PSG layer 16, the photoresist layer 17 is selectively exposed and developed to be removed only at a portion where a channel region is to be formed.

The second PSG layer 16, the nitride layer 15, the oxide layer 14, and the first PSG layer 13 are selectively etched using the selectively exposed and developed photoresist layer 17 as a mask. The semiconductor substrate 11 is exposed.

As shown in FIG. 1D, after removing the photoresist layer 17, an epitaxial layer 18 is grown on the exposed semiconductor substrate 11 and the second PSG layer 16 in the channel region. The epitaxial layer 18 is planarized by a chemical mechanical polishing (CMP) method using the PSG layer 16 as an etching end point.

As shown in FIG. 1E, the polycrystalline silicon layer, the second nitride film 20, and the second photosensitive film 21 in which high concentrations of n-type impurities are implanted on the second PSG layer 16 and the epitaxial layer 18 are sequentially formed. To form.

The second photosensitive film 21 is selectively exposed and developed so that only the portion where the source region is to be formed remains.

Subsequently, the second nitride film 20, the polycrystalline silicon layer, and the second PSG layer 16 are selectively etched using the selectively exposed and developed second photosensitive film 21 as a mask.

Here, the source region 19 is formed by selective etching of the polycrystalline silicon worm.

As shown in FIG. 1F, after removing the second photoresist layer 21, a third nitride layer is formed on the first and second nitride layers 15 and 20, and the third nitride layer is etched back. The third nitride film sidewall 22 is formed on the oxide film 14 on both sides of the source region 19, and then the oxide film 14 is removed.

Here, during the etch back process of the third nitride film, the exposed first nitride film 15 is also selectively removed.

As shown in FIG. 1G, a gate oxide film is grown on the exposed epitaxial layer 18 surface by a thermal oxidation process on the front surface, a second polycrystalline silicon layer is formed on the front surface, and the second polycrystalline silicon layer is deposited on the surface. The back electrode is formed to form the gate electrode 23.

However, in the conventional CMOS transistor and a method of manufacturing the same, since the channel region is not electrically connected to the semiconductor substrate, the semiconductor substrate is floating, so the threshold voltage is unstable and a kink occurs, thereby degrading the characteristics and reliability of the device. There was a problem.

The present invention has been made in order to solve the above-mentioned problems, the CMOS transistor which prevents the semiconductor substrate from floating because the epitaxial layer for forming the channel region is grown after forming a contact that is an electrical connection passage between the channel region and the semiconductor substrate; Its purpose is to provide a process for its preparation.

1A to 1G are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to the prior art.

2 is a cross-sectional view illustrating a CMOS transistor according to an embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an embodiment of the present invention.

<Description of Symbols for Major Parts of Drawings>

31 SOI substrate 32 Silicon substrate

33: buried oxide film 34: first epitaxial layer

35 first nitride film 36 first photosensitive film

37: PSG layer 38: BSG layer

39: second photosensitive film 40: first electrode contact hole

41 second electrode contact hole 42 third photosensitive film

43: drain region of NMOS 44: drain region of PMOS

45: second epitaxial layer 46: channel region of NMOS

47: PMOS channel region 48: p-type well

49: source region of NMOS 50: n-type well

51 source region of PMOS 52 second nitride film

53 gate oxide film 54 gate electrode of NMOS

55: gate electrode of PMOS

The CMOS transistor of the present invention has a first and a second conductivity type well formed adjacent to a surface of a silicon substrate, and first and second electrode contact holes formed on each of the first and second conductivity type wells and are formed on the silicon substrate. A buried oxide film and a first epitaxial layer sequentially stacked on the first and second conductivity type wells, and first and second conductivity type drain regions formed in the first epitaxial layer above each of the first and second conductivity type wells. A channel region of the first and second conductivity type MOSs formed by a process of growing a second epitaxial layer on the second electrode contact hole and the first epitaxial layer adjacent to each of the first and second electrode contact holes, wherein each of the first And gate electrodes of the first and second conductivity type MOSs formed on the first epitaxial layers on both sides of the channel region of the second conductivity type MOS, and the channel regions of the first and second conductivity type MOSs. Formed on the gate electrodes of each of the first and second conductivity type MOSs Is characterized by including the first and second conductivity type source regions.

In the method of manufacturing a CMOS transistor of the present invention, the step of forming a first and second conductivity-type MOS is defined, each step of providing an SOI substrate formed by sequentially buried oxide film and the first epitaxial layer on a silicon substrate, A first insulating film in which a second conductivity type impurity ion is implanted on the SOI substrate at the site where the second conductivity type MOS is to be formed, and a first conductivity type impurity ion is implanted on the SOI substrate and the first insulating film Forming and planarizing the second insulating film, and selectively etching the second insulating film, the first insulating film, the first epitaxial layer, and the buried oxide film at the portion where the second conductive MOS is to be formed to form a first electrode contact hole; Selectively etching the second insulating film, the epitaxial layer and the buried oxide film in the portion where the first conductivity type MOS is to be formed to form a second electrode contact hole, and forming a channel region at the portion where the second conductivity type MOS is to be formed Etching the second insulating film and the first insulating film of the portion to be formed, and etching the second insulating film of the portion where the channel region is to be formed in the portion where the first conductive MOS is to be formed; A second conductive type ion and a first conductive type ion implanted in each of the second insulating layer are implanted into the first epitaxial layer to form first and second conductive type drain regions, and the first and second electrode contact holes Forming a channel region of the first and second conductivity type MOSs by growing a second epitaxial layer on the region where the channel region is to be formed and the region where the source region is to be formed, and removing the first and second insulating layers. Forming a first conductivity well in the surface of the silicon substrate of the site where the second conductivity type MOS is to be formed, and forming a high concentration agent in the second epitaxial layer of the site where the source region on the channel region of the second conductivity type 2 implanting impurity ions Forming a second conductivity type source region, forming a second conductivity type well in the surface of the silicon substrate at the site where the first conductivity type MOS is to be formed, and forming a source region on the channel region of the first conductivity type MOS. Implanting a high concentration of first conductivity type impurity ions into a second epitaxial layer of a region to be formed to form a first conductivity type source region and each of first and second sides of channel regions of each of the first and second conductivity type MOSs And forming gate electrodes of the first and second conductivity type MOSs through the gate insulating layer under the second conductivity type source region.

A preferred embodiment of the CMOS transistor and a method of manufacturing the same according to the present invention as described above will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a CMOS transistor according to an exemplary embodiment of the present invention, and FIGS. 3A to 3H are cross-sectional views illustrating a method of manufacturing a CMOS transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 2, a CMOS transistor according to an exemplary embodiment of the present invention has a p-type well 48 and an n-type well 50 formed adjacent to a surface of a silicon substrate 32, and each of the p-type wells 48 and n. A buried oxide film 33 and a first epitaxial layer 34 having first and second electrode contact holes 40 and 41 formed on the upper side of the type well 50 and sequentially stacked on the silicon substrate 32. ), Drain regions 43 and 44 of NMOS and PMOS formed in the first epitaxial layer 34 above the p-type wells 48 and the n-type wells 50, respectively, and the first and second electrodes An NMOS formed by a process of growing a second epitaxial layer 45 on the contact holes 40 and 41 and the first epitaxial layer 34 adjacent to each of the first and second electrode contact holes 40 and 41; NMOS and PMOS gate electrodes 54 formed on the channel regions 46 and 47 of the PMOS, and the first epitaxial layer 34 on both sides of the NMOS and PMOS channel regions 46 and 47, respectively, with a gate insulating film interposed therebetween. 55, the channel regions 46 and 47 of the respective NMOS and PMOS, NMOS and PMOS source regions 49 and 51 formed on gate electrodes 54 and 55 of NMOS and PMOS.

In the method of manufacturing a CMOS transistor according to an embodiment of the present invention, as shown in FIG. 3A, a first nitride film 35 is formed on a silicon on insulator (SOI) substrate 31 in which portions of NMOS and PMOS are to be defined, respectively. ) And a first photosensitive film 36, and selectively expose and develop the first photosensitive film 36 so that only the portion where the PMOS is to be formed remains.

Here, the silicon on insulator (SOI) substrate 31 is formed by sequentially filling the buried oxide film 33 and the epitaxial layer 34 on the silicon (Si) substrate 32.

Then, the first nitride film 35 of the portion where the NMOS is to be formed is etched using the selectively exposed and developed first photosensitive film 36 as a mask.

As shown in FIG. 3B, the first photosensitive layer 36 is removed and a PSG layer 37 implanted with phosphorus (P) ions is formed on the SOI substrate 31 and the first nitride layer 35.

The PSG layer 37 is planarized by a CMP method using the first nitride film 35 as an etching end point to form a PSG layer 37 on the SOI substrate 31 at the portion where the NMOS is to be formed.

As shown in FIG. 3C, after removing the first nitride layer 35, boron (B) implanted with a boron (B) layer 38 on the SOI substrate 31 and the PSG layer 37. Form and planarize.

After the second photoresist film 39 is coated on the BSG layer 38, the second photoresist film 39 is selectively exposed and developed to be removed only at a portion where a substrate electrode contact is to be formed.

Subsequently, the BSG layer 38, the PSG layer 37, the epitaxial layer 34, and the buried oxide layer 33 are formed at a portion where the NMOS is to be formed using the selectively exposed and developed second photoresist layer 39 as a mask. And selectively etch to form a first electrode contact hole 40, and the BSG layer 38, the epitaxial layer 34 and the buried oxide layer 33 are selectively etched in a portion where the PMOS is to be formed. The hole 41 is formed.

As shown in FIG. 3D, the second photoresist layer 39 is removed, the third photoresist layer 42 is coated on the entire surface including the first and second electrode contact holes 40 and 41, and then the third photoresist layer is formed. The 42 is selectively exposed and developed to be removed only at the site where the channel region is to be formed.

The BSG layer 38 and the PSG layer 37 are selectively etched in the portion where the NMOS is to be formed using the selectively exposed and developed third photoresist layer 42 as a mask, and in the portion where the PMOS is to be formed, The BSG layer 38 is selectively etched.

As shown in FIG. 3E, the third photoresist layer 42 is removed, and phosphorus ions and boron ions implanted into the PSG layer 37 and the BSG layer 38, respectively, are implanted into the first epitaxial layer 34. The entire surface is heat-treated to form the drain region 43 of the NMOS and the drain region 44 of the PMOS.

Then, the second epitaxial layer 45 is grown on the exposed portions of the first and second electrode contact holes 40 and 41 on the silicon substrate 32.

Here, NMOS and PMOS are respectively formed as the second epitaxial layer 45 grown on the selective etching portions of the PSG layer 37 and the BSG layer 38 including the first and second electrode contact holes 40 and 41. Channel regions 46 and 47.

As shown in FIG. 3F, the PSG layer 37 and the BSG layer 38 are removed, and a fourth photosensitive film (not shown) is applied to the entire surface including the second epitaxial layer 45. 4 The photoresist is selectively exposed and developed so as to be removed only at the site where the NMOS is to be formed.

Then, the p-type impurity ions are implanted into the surface of the silicon substrate 32 using the selectively exposed and developed fourth photoresist film to form a p-type well 48, and other than the channel region 46 of the NMOS. After the high concentration n-type impurity ions are implanted into the 2 epitaxial layer 45 to form the source region 49 of the NMOS, the fourth photoresist layer is removed.

Subsequently, the photo process is repeated to form n-type wells 50 by implanting n-type impurity ions into the surface of the silicon substrate 32 at the portion where the PMOS is to be formed, and to form an n-type well 50. High concentration p-type impurity ions are implanted into the epitaxial layer 45 to form the source region 51 of the PMOS.

As shown in FIG. 3G, the second nitride film 52 and the fifth photoresist film (not shown) are formed on the entire surface, and the fifth photoresist film is selectively exposed and developed to be removed only at the portion where the NMOS is to be formed.

The gate oxide film 53 is grown on the exposed first and second epitaxial layers 34 and 45 by thermal oxidation using the selectively exposed and developed fifth photoresist film as a mask.

Subsequently, a second polycrystalline silicon layer in which n-type impurities are implanted is formed on the entire surface including the gate oxide layer 53, and is selectively etched by a photo process to form an NMOS source region 49 on both sides of the channel region 46 of the NMOS. NMOS gate electrode 54 is formed below.

Instead of the gate oxide film 53, one of tantalum (Ta), hafnium (Hf), and zirconium (Zr) having a high dielectric constant may be formed.

As shown in FIG. 3H, the second nitride film 52 is removed, and the same method as that of forming the gate electrode 54 of the NMOS is repeated, so that the source region 51 of the PMOS on both sides of the channel region 47 of the PMOS is repeated. On the lower side, a gate electrode 55 of the PMOS is formed.

In the CMOS transistor of the present invention and a method of manufacturing the same, an epitaxial layer for forming a channel region is grown after forming a contact, which is an electrical connection passage between a channel region and a semiconductor substrate, thereby preventing the semiconductor substrate from floating, thereby stabilizing a threshold voltage. Since it prevents the occurrence of a kink phenomenon, there is an effect to improve the characteristics and reliability of the device.

Claims (3)

First and second conductivity wells formed adjacent to the silicon substrate surface; A buried oxide film and a first epitaxial layer having first and second electrode contact holes formed on each of the first and second conductive wells and sequentially stacked on the silicon substrate; First and second conductivity type drain regions formed in the first epitaxial layer above each of the first and second conductivity type wells; Channel regions of the first and second conductivity type MOSs formed by a process of growing a second epitaxial layer on the first and second electrode contact holes and on the first epitaxial layer adjacent to each of the first and second electrode contact holes. ; Gate electrodes of the first and second conductivity type MOSs formed on the first epitaxial layers on both sides of the channel region of each of the first and second conductivity type MOSs with a gate insulating film interposed therebetween; And a channel region of each of the first and second conductivity type MOSs and a first and second conductivity type source region formed on the gate electrode of each of the first and second conductivity type MOSs. Providing an SOI substrate on which a portion of the first and second conductivity type MOSs is to be defined, wherein a buried oxide film and a first epitaxial layer are sequentially stacked on a silicon substrate; A first insulating film in which a second conductivity type impurity ion is implanted on the SOI substrate at the site where the second conductivity type MOS is to be formed, and a first conductivity type impurity ion is implanted on the SOI substrate and the first insulating film Forming and planarizing an insulating film; Selectively etching the second insulating film, the first insulating film, the first epitaxial layer, and the buried oxide film in the portion where the second conductivity type MOS is to be formed to form a first electrode contact hole, and the portion where the first conductivity type MOS is to be formed. Selectively etching the second insulating film, the epitaxial layer and the buried oxide film to form a second electrode contact hole; The second insulating film and the first insulating film of the portion where the channel region is to be formed are etched in the portion where the second conductivity type MOS is to be formed, and the second insulating layer of the portion where the channel region is to be formed in the portion where the first conductivity type MOS is to be formed. Etching; Implanting second conductivity type ions and first conductivity type ions respectively implanted into the first and second insulating layers by heat treatment on the entire surface to form first and second conductivity type drain regions; ; Forming a channel region of the first and second conductivity type MOSs by growing a second epitaxial layer in the region where the first and second electrode contact holes and the channel region are to be formed and the region where the source region is to be formed; Removing the first and second insulating films; Forming a first conductivity well in a silicon substrate surface of a portion where the second conductivity type MOS is to be formed, and a second high concentration in the second epitaxial layer of the portion where the source region on the channel region of the second conductivity type MOS is to be formed; Implanting conductive impurity ions to form a second conductive source region; A second conductive well is formed in the surface of the silicon substrate of the portion where the first conductivity type MOS is to be formed, and a high concentration first is formed in the second epitaxial layer of the portion where the source region on the channel region of the first conductivity type MOS is to be formed. Implanting conductive impurity ions to form a first conductive source region; Forming a gate electrode of the first and second conductivity type MOSs through a gate insulating layer under each of the first and second conductivity type source regions on both sides of the channel region of each of the first and second conductivity type MOSs; Method of manufacturing a CMOS transistor, characterized in that. The method of claim 2, And the gate insulating film is formed of an oxide film or one of tantalum, hafnium and zirconium having a high dielectric constant.