JPS57143854A - Complementary type metal oxide semiconductor device and its manufacture - Google Patents

Complementary type metal oxide semiconductor device and its manufacture

Info

Publication number
JPS57143854A
JPS57143854A JP56028212A JP2821281A JPS57143854A JP S57143854 A JPS57143854 A JP S57143854A JP 56028212 A JP56028212 A JP 56028212A JP 2821281 A JP2821281 A JP 2821281A JP S57143854 A JPS57143854 A JP S57143854A
Authority
JP
Japan
Prior art keywords
type
gate electrodes
manufacture
semiconductor device
metal oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56028212A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kobayashi
Takeo Kondo
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56028212A priority Critical patent/JPS57143854A/en
Publication of JPS57143854A publication Critical patent/JPS57143854A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce parasitic capacity, and to increase working speed by forming reverse conduction type layers deeper than source-drains under the gate electrodes of each FET of the C-MOS. CONSTITUTION:A P<-> type well region 14 is formed into an N<-> type Si substrate 11, a field oxide film 21 and each inversion preventive layer are formed, a gate oxide film is molded, and an impurity is implanted using a resist film as a mask before forming the gate electrodes 27, 28. The comparatively deep P<+> type region 24 and N<+> type region 26 are formed, the gate electrodes 27, 28 are formed, and the source-drain regions 30, 31, 34, 35 are formed through ion implantation while using the electrodes the as masks. Accordingly, the parasitic capacity can be reduced because the impurity concentration of the substrate and the well region can be lowered, and speed can be increased because channel length can be shortened.
JP56028212A 1981-02-27 1981-02-27 Complementary type metal oxide semiconductor device and its manufacture Pending JPS57143854A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56028212A JPS57143854A (en) 1981-02-27 1981-02-27 Complementary type metal oxide semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56028212A JPS57143854A (en) 1981-02-27 1981-02-27 Complementary type metal oxide semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS57143854A true JPS57143854A (en) 1982-09-06

Family

ID=12242333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56028212A Pending JPS57143854A (en) 1981-02-27 1981-02-27 Complementary type metal oxide semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS57143854A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123055A (en) * 1983-12-07 1985-07-01 Fujitsu Ltd Semiconductor device and manufacture thereof
EP0178991A2 (en) * 1984-10-13 1986-04-23 Fujitsu Limited A complementary semiconductor device having high switching speed and latchup-free capability
US5679588A (en) * 1995-10-05 1997-10-21 Integrated Device Technology, Inc. Method for fabricating P-wells and N-wells having optimized field and active regions

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123055A (en) * 1983-12-07 1985-07-01 Fujitsu Ltd Semiconductor device and manufacture thereof
EP0178991A2 (en) * 1984-10-13 1986-04-23 Fujitsu Limited A complementary semiconductor device having high switching speed and latchup-free capability
US4893164A (en) * 1984-10-13 1990-01-09 Fujitsu Limited Complementary semiconductor device having high switching speed and latchup-free capability
US5679588A (en) * 1995-10-05 1997-10-21 Integrated Device Technology, Inc. Method for fabricating P-wells and N-wells having optimized field and active regions
US5926704A (en) * 1995-10-05 1999-07-20 Integrated Device Technology, Inc. Efficient method for fabricating P-wells and N-wells

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