JPS57104258A - Metal oxide semiconductor - Google Patents
Metal oxide semiconductorInfo
- Publication number
- JPS57104258A JPS57104258A JP18038180A JP18038180A JPS57104258A JP S57104258 A JPS57104258 A JP S57104258A JP 18038180 A JP18038180 A JP 18038180A JP 18038180 A JP18038180 A JP 18038180A JP S57104258 A JPS57104258 A JP S57104258A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- shaped
- impurity
- concentration
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 239000012535 impurity Substances 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
Abstract
PURPOSE:To obtain a MOSFET having excellent output characteristics and high dielectric resistance by making higher the concentration of the P type impurity of a P<-> substrate under a gate, a source field plate and one part of an offset gate. CONSTITUTION:Acceptor impurity ions are implanted selectively into the P<-> type Si substrate 1b having the low concentration of the impurity, and a P<-> well 1a having slightly higher impurity concentration is formed. An N<-> type well 3a is shaped to a drain section through ion implantation. A SiO2 mask is removed, and a thin SiO2 film 4 for the gate is formed. A gate electrode 5 of a poly Si layer is shaped, the high dielectric resisting layer (the offset gate) 6 is molded through ion implantation, a CVD.SiO2 film 7 is formed, and an N<+> source region 2 and an N<+> drain region 3 are shaped. The source field plate 9 and an electrode are formed through the evaporation of Al and a selective etching process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18038180A JPS57104258A (en) | 1980-12-22 | 1980-12-22 | Metal oxide semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18038180A JPS57104258A (en) | 1980-12-22 | 1980-12-22 | Metal oxide semiconductor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57104258A true JPS57104258A (en) | 1982-06-29 |
JPS6364909B2 JPS6364909B2 (en) | 1988-12-14 |
Family
ID=16082234
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18038180A Granted JPS57104258A (en) | 1980-12-22 | 1980-12-22 | Metal oxide semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57104258A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01162372A (en) * | 1987-12-18 | 1989-06-26 | Matsushita Electron Corp | Mis transistor |
JPH03227572A (en) * | 1989-07-04 | 1991-10-08 | Fuji Electric Co Ltd | Mos semiconductor device |
-
1980
- 1980-12-22 JP JP18038180A patent/JPS57104258A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01162372A (en) * | 1987-12-18 | 1989-06-26 | Matsushita Electron Corp | Mis transistor |
JPH03227572A (en) * | 1989-07-04 | 1991-10-08 | Fuji Electric Co Ltd | Mos semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6364909B2 (en) | 1988-12-14 |
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