JPS5617026A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5617026A
JPS5617026A JP9360379A JP9360379A JPS5617026A JP S5617026 A JPS5617026 A JP S5617026A JP 9360379 A JP9360379 A JP 9360379A JP 9360379 A JP9360379 A JP 9360379A JP S5617026 A JPS5617026 A JP S5617026A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
smooth
substrate
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9360379A
Other languages
Japanese (ja)
Inventor
Hirokazu Miyoshi
Kazuo Mizuguchi
Hiroji Harada
Shinichi Sato
Sumio Nomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9360379A priority Critical patent/JPS5617026A/en
Publication of JPS5617026A publication Critical patent/JPS5617026A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To prevent disconnection of a wire in a semiconductor device by irradiating P ion beam to the surface of an oxide film to thereby smooth the surface of the film at low temperature without increasing the P density of the oxide film. CONSTITUTION:A source 2 and a drain 3 are formed in an Si substrate 1, and a gate electrode 5 is formed on the SiO2 film 4. After forming an SiO2 film 6 at approx. 450 deg.C by the reaction of SiH4+O2, P ion beam 8 is irradiated thereto to raise the surface temperature only so as to smooth the surface thereof. Since the accelerating voltage is low in this case, the ions are not implanted to the substrate 1, the P ion is implanted slightly into the film 6 to form a PSG so as to lower the melting point thereof. Since this configuration can eliminate the step of flattening the surface at high temperature, it can remarkably improve the reliability of the semiconductor device.
JP9360379A 1979-07-20 1979-07-20 Manufacture of semiconductor device Pending JPS5617026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9360379A JPS5617026A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9360379A JPS5617026A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5617026A true JPS5617026A (en) 1981-02-18

Family

ID=14086894

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9360379A Pending JPS5617026A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617026A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007324573A (en) * 2006-05-30 2007-12-13 Sharp Corp Compound semiconductor-on-silicon wafer with thermally softened insulator
US7696671B2 (en) 2004-10-15 2010-04-13 Olympus Medical Systems Corporation Array ultrasonic transducer having piezoelectric devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696671B2 (en) 2004-10-15 2010-04-13 Olympus Medical Systems Corporation Array ultrasonic transducer having piezoelectric devices
JP2007324573A (en) * 2006-05-30 2007-12-13 Sharp Corp Compound semiconductor-on-silicon wafer with thermally softened insulator

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