JPS561572A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS561572A
JPS561572A JP7612779A JP7612779A JPS561572A JP S561572 A JPS561572 A JP S561572A JP 7612779 A JP7612779 A JP 7612779A JP 7612779 A JP7612779 A JP 7612779A JP S561572 A JPS561572 A JP S561572A
Authority
JP
Japan
Prior art keywords
film
sio2 film
region
polycrystalline
glass layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7612779A
Other languages
Japanese (ja)
Other versions
JPS6159669B2 (en
Inventor
Eizo Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7612779A priority Critical patent/JPS561572A/en
Publication of JPS561572A publication Critical patent/JPS561572A/en
Publication of JPS6159669B2 publication Critical patent/JPS6159669B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To provide a semiconductor device having high reliability by forming a polycrystalline Si gate electrode when forming an MOS type transistor, coating a glass layer containing boron thereon, and heat treating to alter it into a thick SiO2 film so as to form source and drain regions at both sides of the SiO2 film. CONSTITUTION:A thick field SiO2 film 13 is formed at the periphery of a P-type Si substrate 12, a thin SiO2 film 14 is formed on the substrate 12 at the portion surrounded by the film 13, a polycrystalline Si gate electrode 16 is formed on the central region of the film 14, and a polycrystalline Si wiring layer 17 is formed on the film 13 to surround only the electrode 16 with a glass layer 18 including boron. Then, the layer 18 as a mask it is etched to form openings 19 in the film 14 at both sides thereof, and to heat treat it to alter the glass layer 18 into a thick SiO2 film 20. Thereafter, ion is implanted through the thin SiO2 film 21 produced in the opening 19 to form an N-type region 21, to again heat treat it to diffuse the region 21 so as to form N-type source and drain regions 22. In this manner, no withstand voltage is decreased even if the depth of the region 22 is increased.
JP7612779A 1979-06-15 1979-06-15 Manufacture of semiconductor device Granted JPS561572A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7612779A JPS561572A (en) 1979-06-15 1979-06-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7612779A JPS561572A (en) 1979-06-15 1979-06-15 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS561572A true JPS561572A (en) 1981-01-09
JPS6159669B2 JPS6159669B2 (en) 1986-12-17

Family

ID=13596257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7612779A Granted JPS561572A (en) 1979-06-15 1979-06-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS561572A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH023226A (en) * 1988-06-20 1990-01-08 Fujitsu Ltd Manufacture of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350497A (en) * 1986-08-18 1988-03-03 Crown Denken:Kk Method for coloring titanium material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH023226A (en) * 1988-06-20 1990-01-08 Fujitsu Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6159669B2 (en) 1986-12-17

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