JPS54161282A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS54161282A JPS54161282A JP7049878A JP7049878A JPS54161282A JP S54161282 A JPS54161282 A JP S54161282A JP 7049878 A JP7049878 A JP 7049878A JP 7049878 A JP7049878 A JP 7049878A JP S54161282 A JPS54161282 A JP S54161282A
- Authority
- JP
- Japan
- Prior art keywords
- film
- regions
- substrate
- sio
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To obtain a short-channel element with excellent electric characteristics by forming a step between source and drain regions, by carrying out shallow diffusion where an insulating film near a gate electrode resides and deep diffusion where the substrate surface outside of it is exposed.
CONSTITUTION: At both edges of P--type Si substrate 1, thick field SiO2 films 2 are formed and on substrate 1 surrounded with them, thin gate SiO2 film 3 is bonded. On the center region of film 3, poly-crystal Si gate electrode 4 is provided, its surface and flank are covered with resist film 5, and the exposed part of film 3 is removed by etching. Through ion injection, N+-type source region 6 and N+-type drain region 7 are formed inside of substrate 1 and electrode 4 is made conductive, but the depths of regions 6 and 7 right under residual film 3 projecting under electrode 4 at this time become shallower. In this way, a step is given between regions 6 and 7, a window is made in SiO2 film 8 bonded on the entire surface, and electrodes 9 and 10 are provided to regions 6 and 7 respectively.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7049878A JPS54161282A (en) | 1978-06-12 | 1978-06-12 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7049878A JPS54161282A (en) | 1978-06-12 | 1978-06-12 | Manufacture of mos semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54161282A true JPS54161282A (en) | 1979-12-20 |
Family
ID=13433241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7049878A Pending JPS54161282A (en) | 1978-06-12 | 1978-06-12 | Manufacture of mos semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54161282A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| JPH07169975A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07169974A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2010098321A (en) * | 1993-09-20 | 2010-04-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1978
- 1978-06-12 JP JP7049878A patent/JPS54161282A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4837180A (en) * | 1987-07-09 | 1989-06-06 | Industrial Technology Research Institute | Ladder gate LDDFET |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| JPH07169975A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| JPH07169974A (en) * | 1993-09-20 | 1995-07-04 | Semiconductor Energy Lab Co Ltd | Semiconductor device and its manufacture |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6867431B2 (en) * | 1993-09-20 | 2005-03-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| JP2010098321A (en) * | 1993-09-20 | 2010-04-30 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| JP4657361B2 (en) * | 1993-09-20 | 2011-03-23 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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