JPS55154769A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55154769A
JPS55154769A JP6299679A JP6299679A JPS55154769A JP S55154769 A JPS55154769 A JP S55154769A JP 6299679 A JP6299679 A JP 6299679A JP 6299679 A JP6299679 A JP 6299679A JP S55154769 A JPS55154769 A JP S55154769A
Authority
JP
Japan
Prior art keywords
film
region
sio2
type
coated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6299679A
Other languages
Japanese (ja)
Other versions
JPS6161268B2 (en
Inventor
Hideto Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6299679A priority Critical patent/JPS55154769A/en
Publication of JPS55154769A publication Critical patent/JPS55154769A/en
Publication of JPS6161268B2 publication Critical patent/JPS6161268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

PURPOSE:To enhance the integrating degree of an n-channel type Si gate MOS semiconductor device by employing a PSG film including impurity when forming a diffused region in a semiconductor substrate. CONSTITUTION:A thick field SiO2 film 22 is formed at the peripheral edge of a p- type Si substrate 21, a thin gate SiO2 film 23 is coated on the portion therebetween, a polycrystalline Si gate electrode 24 is formed thereon, with the electrode 24 as a mask ion is implanted thereto to form n-type source and drain regions 25a, 25b, and the film 23 is then removed thereon. Then, a PSG film 26 is coated on the entire surface, an SiO2 film 28a is formed at the center in the recess corresponding to the region 25a of the recess formed in accordance with the shape of the lower side, an SiO2 film 28b extended from the film 26 is formed in the recess corresponding to the region 25b, heat treated to extend an SiO2 film 30a continued to the film 22 at the side of the region 25a and SiO2 films 30b and 30c at both sides of the film 23. Simultaneously, impurity in the film 26 is diffused, and a deep n-type region 29a and 29b integral with one another are formed penetrating through the regions 25a and 25b.
JP6299679A 1979-05-22 1979-05-22 Manufacture of semiconductor device Granted JPS55154769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6299679A JPS55154769A (en) 1979-05-22 1979-05-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6299679A JPS55154769A (en) 1979-05-22 1979-05-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55154769A true JPS55154769A (en) 1980-12-02
JPS6161268B2 JPS6161268B2 (en) 1986-12-24

Family

ID=13216484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6299679A Granted JPS55154769A (en) 1979-05-22 1979-05-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55154769A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935474A (en) * 1982-08-23 1984-02-27 Toshiba Corp Manufacture of semiconductor device
JPS5935475A (en) * 1982-08-23 1984-02-27 Toshiba Corp Manufacture of semiconductor device
US6022781A (en) * 1994-12-28 2000-02-08 International Business Machines Corporation Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179060U (en) * 1988-06-10 1989-12-21

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5935474A (en) * 1982-08-23 1984-02-27 Toshiba Corp Manufacture of semiconductor device
JPS5935475A (en) * 1982-08-23 1984-02-27 Toshiba Corp Manufacture of semiconductor device
US6022781A (en) * 1994-12-28 2000-02-08 International Business Machines Corporation Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack

Also Published As

Publication number Publication date
JPS6161268B2 (en) 1986-12-24

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