JPS5662333A - Mos type semiconductor memory device and production thereof - Google Patents
Mos type semiconductor memory device and production thereofInfo
- Publication number
- JPS5662333A JPS5662333A JP13839279A JP13839279A JPS5662333A JP S5662333 A JPS5662333 A JP S5662333A JP 13839279 A JP13839279 A JP 13839279A JP 13839279 A JP13839279 A JP 13839279A JP S5662333 A JPS5662333 A JP S5662333A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- memory cell
- oxide film
- section
- inclination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76267—Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Abstract
PURPOSE:To improve the memory retaining property of a memory cell by providing a buried insulator layer for electrically separating a memory cell array section from a peripheral circuit section in such a manner that the end thereof is positioned on the surface of a substrate corresponding to a field region. CONSTITUTION:A silicon oxide film 11 is formed on the surface of a substrate 1. Then, a resist film 12 having a window is provided at a memory cell array section and a window is etched away in the oxide film 11. At this point, the open end section of the oxide film 11 is given an inclination of about 45 deg., for instance. With the oxide film 11 having such an inclination as an ion implantation mask, oxygen is implanted. Subsequently, heat treatment is made to convert the ion implanted layer into a buried insulator layer 3 whereby a construction is obtained to separate the substrate 12 of the memory cell accurately from the substrate 1 in a peripheral circuit section. Thereafter, a MOS device necessary for each substrate area is formed to complete a dynamic RAM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13839279A JPS5662333A (en) | 1979-10-26 | 1979-10-26 | Mos type semiconductor memory device and production thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13839279A JPS5662333A (en) | 1979-10-26 | 1979-10-26 | Mos type semiconductor memory device and production thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5662333A true JPS5662333A (en) | 1981-05-28 |
Family
ID=15220862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13839279A Pending JPS5662333A (en) | 1979-10-26 | 1979-10-26 | Mos type semiconductor memory device and production thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5662333A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58106858A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Semiconductor integrated circuit |
JPS59181050A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS6072243A (en) * | 1983-09-28 | 1985-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor ic device |
JPS6242556A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS632350A (en) * | 1986-06-20 | 1988-01-07 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01251636A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of dielectric isolation wafer |
US7265017B2 (en) | 2003-07-31 | 2007-09-04 | Kabushiki Kaisha Toshiba | Method for manufacturing partial SOI substrates |
JP2010130027A (en) * | 2008-12-01 | 2010-06-10 | Samsung Electronics Co Ltd | Semiconductor device, and method for manufacturing the same |
-
1979
- 1979-10-26 JP JP13839279A patent/JPS5662333A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58106858A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Semiconductor integrated circuit |
JPS59181050A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH0526346B2 (en) * | 1983-03-31 | 1993-04-15 | Tokyo Shibaura Electric Co | |
JPS6072243A (en) * | 1983-09-28 | 1985-04-24 | Matsushita Electric Ind Co Ltd | Semiconductor ic device |
JPS6242556A (en) * | 1985-08-20 | 1987-02-24 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS632350A (en) * | 1986-06-20 | 1988-01-07 | Fujitsu Ltd | Manufacture of semiconductor device |
JPH01251636A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Manufacture of dielectric isolation wafer |
US7265017B2 (en) | 2003-07-31 | 2007-09-04 | Kabushiki Kaisha Toshiba | Method for manufacturing partial SOI substrates |
JP2010130027A (en) * | 2008-12-01 | 2010-06-10 | Samsung Electronics Co Ltd | Semiconductor device, and method for manufacturing the same |
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