JPH0526346B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device.
It is related to the manufacturing method of RAM and static RAM.

[Technical background of the invention]

The properties of wafers suitable for large-capacity memories, especially dynamic RAM, include the following.

The wafer must have high flatness for good microfabrication.

The specific resistance of the wafer surface must be uniform to suppress variations in threshold voltage.

The surface of the wafer should be free of defects to enhance the memory retention properties of the storage capacitor.

The lifetime of the carrier inside the wafer is short in order to prevent storage deterioration due to the carrier injected into the wafer (measures against soft errors and hot electrons).

When current flows through the wafer, the specific resistance of the wafer is small in order to suppress local fluctuations in potential due to voltage drop due to the wafer resistance.

Conventionally, wafers that meet the above conditions are
There is an epitaxial wafer. A typical example of this is shown in FIG. That is, a P type single crystal silicon layer 2 having a specific resistance of 10 Ωcm and a film thickness of about 10 μm, for example, is epitaxially grown on a P ⁺ type silicon wafer (substrate) 1 having a low specific resistance of 0.01 μm. At this time, the substrate 1 is brought into a supersaturated state by containing oxygen of 10 ¹⁷ /cm ³ or more, and the oxygen is precipitated by subsequent heat treatment, and this is used as a nucleus to generate micro defects 3, forming a micro defect region only in the substrate 1 region. is formed. Such a wafer is considered to satisfy at least the above conditions, and has been considered to be a wafer suitable for high-density LSI such as dynamic RAM.

[Problems with background technology]

When we prototyped a dynamic RAM using the epitaxial wafer described above and evaluated it by comparing it with a prototype made using a bulk wafer with a resistivity of 10 Ωcm without epitaxial growth, we found that many of its characteristics were
We were able to obtain results equivalent to or better than bulk wafers. However, regarding soft errors caused by alpha rays, worse results were obtained compared to bulk wafers, even though epitaxial wafers have micro defects on their substrates (bulk wafers do not have micro defects). The reason for this is shown in Figures 2 to 4.
This will be explained using figures.

^The potential distribution in the depth direction of the ^epitaxial wafer is as shown in FIG.
There is a potential barrier due to the difference in Fermi levels. Therefore, most of the electrons generated in the P-type single crystal silicon layer 2 by the α rays are reflected by this barrier (as shown in FIG. 3). Therefore, these electrons have a low probability of entering the P ⁺ type substrate 1 and are less likely to be captured by the minute defects 3 existing in the P ⁺ type substrate 1. On the other hand, the carrier lifetime of the P-type single crystal silicon layer 2 is usually better than that of a bulk wafer. Therefore, many of the electrons generated in the P-type single-crystal silicon layer 2 do not die and are transferred to the storage storage charge storage capacitor (for example, the polycrystalline silicon electrode 4 as shown in FIG. 4) provided on the surface of the silicon layer 2.
and oxide film 5, and a positive potential is applied to the electrode 4)
This results in poor memory retention and soft errors.

[Purpose of the invention]

The present invention aims to provide a method for manufacturing a semiconductor device such as a semiconductor memory which has excellent memory retention characteristics, stability of substrate potential, and excellent soft error resistance.

[Summary of the invention]

The present invention provides a structure in which micro defects are present in at least a single crystal semiconductor layer on a single crystal semiconductor substrate, and in particular, by making micro defects exist in a region including the interface between the substrate and the semiconductor layer, soft error resistance can be improved. The main objective is to improve the

[Embodiments of the invention]

Next, a manufacturing method illustrating an embodiment of the present invention will be described.

Example 1 (i) First, oxygen is supersaturated (for example, 10 ¹⁸ /
cm ³ ), P ⁺ type silicon substrate 11 with a specific resistance of 0.01Ωcm
A P-type first single crystal silicon layer 12 having a thickness of about 1 μm and a specific resistance of about 10 Ωcm was epitaxially grown thereon (as shown in FIG. 5a).

(ii) Oxygen was then ion-implanted into the first single crystal silicon layer 12 three times at acceleration voltages of 120 keV, 220 keV, and 340 keV, each at a dose of 1×10 ¹⁵ /cm ² (as shown in FIG. 5b). By such ion implantation, oxygen is distributed almost uniformly in the P-type first single crystal silicon layer 12. Note that in this step, the acceleration voltage may be changed continuously, or ion implantation may be performed once in some cases.

(iii) Next, on the first single-crystal silicon layer 12, a layer with a thickness of approximately
A P-type second single crystal silicon layer 13 having a thickness of 5 μm and a specific resistance of about 10 Ωcm was epitaxially grown (as shown in FIG. 5c).

(iv) Next, heat treatment was performed at a temperature of, for example, 800° C. for 4 hours. This heat treatment may be either oxidizing or non-oxidizing. Through this heat treatment, supersaturated oxygen precipitates in regions containing supersaturated oxygen (substrate 11, first single crystal silicon layer 12), and microdefects are nucleated. Subsequently, a field oxide film 14 is formed on the second single crystal silicon layer 13 according to a conventional method, and this field oxide film 14 is
memory cells are formed in island regions separated by
MOS dynamic RAM was manufactured (Fig. 5d)
(Illustrated). During the heat treatment during the manufacturing process of this RAM (particularly the heat treatment at 900°C for about 10 hours for field formation), P ⁺
Micro defects 15 are generated in the mold silicon substrate 11 and the first single crystal silicon layer 12. In addition,
Reference numeral 16 in FIG. 5d is a capacitor electrode provided in an island region separated by a field oxide film 14 with a thin oxide film 17 interposed therebetween. Reference numeral 18 in the figure denotes a transfer gate electrode 21 whose part is located on the surface of the second single crystal silicon layer 13 via the gate oxide film 19 and whose other end extends onto the capacitor electrode 16 via the insulating film 20. is an interlayer insulating film. Further, 22 ₁ , 22 ₂ , and 22 ₃ in the figure are Al wirings connected to the capacitor electrode 16, the transfer gate electrode 18, and the n ⁺ layer 23 formed on the second single crystal silicon layer 13, respectively.

Therefore, the MOS dynamic RAM of the present invention
is a P ⁺ type silicon substrate 11 as shown in Fig. 5d.
Since it has a structure in which micro defects 15 exist on the silicon layer side from the interface between the P-type single crystal silicon layers 12 and 13, various effects as described below can be exhibited.

(a) Before the electrons generated by the α rays are reflected by the P ⁺ -P potential barrier at the interface between the substrate 11 and the single crystal silicon layers 12 and 13, the micro defects 15 existing in the first single crystal silicon layer 12... It is absorbed by... As a result, it is possible to eliminate the drawback of increased soft errors due to the structure in which a P type single crystal silicon layer is epitaxially grown on a P ⁺ type silicon substrate.

(b) The first single ^- crystal silicon layer 12 is
Soft error resistance due to the presence of micro defects 15 . . . can be improved. That is, since the specific resistance of the silicon substrate 11 can be lowered, potential fluctuations due to substrate current can be suppressed. In addition, since micro defects 15 exist in the silicon substrate 11 and the first single crystal silicon layer 12 at its interface, they become a nucleus for gettering of contaminants such as metals (intensive gettering), and the second single crystal The lifetime of the surface of the silicon layer 13 can be improved.

In Example 1, the depth from the surface of the single-crystal silicon layer to the region where the micro-defect exists is such that the depletion layer extending from the element formed on the surface of the single-crystal silicon layer reaches the region of the micro-defect. It is desirable to choose not to do so.

By controlling the thickness of the first single crystal silicon layer in Example 1 and the acceleration voltage during ion implantation into this silicon layer, the interface of the first single crystal silicon layer 12 can be adjusted as shown in FIG. 6, for example. It is possible to create a structure in which micro defects 15 exist on the upper surface side away from the surface.

In Example 1, if the oxygen concentration in the P ⁺ type silicon substrate is less than 10 ¹⁷ /cm ³ , the density of micro defects in the substrate can be suppressed.

In Example 1 above, supersaturated oxygen was included.
Before epitaxially growing a P type first single crystal silicon layer on a P ⁺ type silicon substrate, heat treatment may be performed to generate micro defect nuclei or micro defects in the substrate. Further, the first single crystal silicon layer may also be subjected to heat treatment to generate micro defect nuclei or micro defects in the single crystal silicon layer before epitaxially growing the P-type second single crystal silicon layer. Of course, microdefect nuclei or microdefects may be simultaneously generated in the P ⁺ type silicon substrate in this step.

Example 2 (i) First, oxygen is supersaturated (for example, 10 ¹⁸ /
cm ³ ), P ⁺ type silicon substrate 11 with a specific resistance of 0.01Ωcm
contains supersaturated oxygen (e.g. 10 ¹⁸ /cm ³ ),
P-type single crystal silicon layer 24 with specific resistance of about 10Ωcm
was epitaxially grown to a thickness of about 8 μm (as shown in Figure 7a).

(ii) Then, in a non-oxidizing atmosphere at 800°C,
Heat treatment was performed for about 5 hours. At this time, supersaturated oxygen in the substrate 11 and the single-crystal silicon layer 24 precipitates, generating nuclei of micro defects. Next, 1100
Heat treatment was performed for 20 minutes to 1 hour in a non-oxidizing atmosphere at .degree. At this time, the single crystal silicon layer 24
The nuclei of micro defects near the surface of the single crystal silicon layer 24 escape to the outside (outer diffusion) to a depth of 4 to 5 μm from the surface of the single crystal silicon layer 24.
A defect-free region 25 is formed in a portion extending over (as shown in FIG. 7b).

(iii) Next, as in Example 1, a single crystal silicon layer 2 is formed.
In the heat treatment process for forming a memory cell in the defect-free region 25 of No. 4, micro defects 15 are formed in the substrate 11 centering around the core of the micro defects, and in the single crystal silicon layer 24 approximately 2 to 3 μm from the surface (interface) of the substrate 11. Also, micro defects 15... are formed, and the MOS
A dynamic RAM was manufactured (as shown in Figure 7c).

The MOS dynamic RAM of the second embodiment can improve the soft error resistance as in the first embodiment, and since the memory cells are formed in the defect-free region 25, the memory retention characteristics can be further improved.

In the above Example 2, high-temperature heat treatment at 1100°C is first performed to outer diffuse supersaturated oxygen near the surface of the P-type single crystal silicon layer, and then low-temperature heat treatment at around 800°C is performed to diffuse the supersaturated oxygen near the surface of the P-type single crystal silicon layer. Defect nucleation may also be performed. This heat treatment may be performed using an energy beam such as a laser beam, an electron beam, or flash light.

Example 3 (i) First, oxygen is supersaturated (for example, 10 ¹⁸ /
cm ³ ), P ⁺ type silicon substrate 11 with a specific resistance of 0.01Ωcm
was prepared and heated in an oxygen atmosphere at 800℃ for 4 hours.
After performing heat treatment for a time to generate nuclei of micro defects in the substrate 11, heat treatment is performed for 10 hours in an oxygen atmosphere at 900°C to generate micro defects 15... around the nuclei in the substrate 11. (as shown in Figure 8a).

(ii) Next, a P-type first single crystal silicon layer 12' containing supersaturated oxygen (for example, 10 ¹⁸ /cm ³ ) and having a specific resistance of 10 Ωcm is epitaxially grown on the surface of the substrate 11 to a thickness of about 1 μm. (as shown in Figure 8b).

(iii) Next, a P-type second layer with a thickness of about 5 μm and a specific resistance of about 10 Ωcm is formed on the first single crystal silicon layer 12'.
A single crystal silicon layer 13 was grown epitaxially (as shown in FIG. 8c).

(iv) Next, a heat treatment is performed for about 2 to 5 hours in a non-oxidizing atmosphere at, for example, 800° C. to precipitate supersaturated oxygen in the first single crystal silicon layer 12' and generate nuclei of micro defects. Continuing, as in Example 1, in the heat treatment process for forming memory cells in the second single crystal silicon layer 13, microdefect nuclei in the first single crystal silicon layer 12' are centered in the silicon layer 12'. Micro defects 15... were generated and MOS dynamic RAM was manufactured (8th
Figure d shown).

Similar to the first embodiment, the MOS dynamic RAM of the third embodiment has improved soft error resistance.

In Example 3 above, micro defects were generated in the first single crystal silicon layer after the epitaxial growth of the second single crystal silicon layer, but micro defects were generated before the growth of the second single crystal silicon layer. It's okay.

Further, in Examples 1 to 3 above, a P ⁺ type silicon substrate is used as a base and a single crystal silicon layer is formed thereon, but the present invention is not limited thereto. For example, as shown in Figure 9, a single crystal insulating substrate (sapphire substrate, etc.)
A P-type single crystal silicon layer 24 may be epitaxially grown on the sapphire substrate 26, and micro defects 15 may be present in the vicinity of the silicon layer 24 at the interface of the sapphire substrate 26. In this case, micro defects may be generated in the single crystal silicon layer a little distance from the interface of the sapphire substrate. Further, as shown in FIG. 10, an oxide film 28 is formed on the surface of a P-type silicon substrate 27, a single crystal silicon layer 29 is provided on this, and minute defects 1 are formed near the silicon layer 29 at the interface of the oxide film 28.
5... may exist. In this case, since it is not possible to epitaxially grow a single crystal silicon layer on the oxide film 28, a polycrystalline silicon layer or an amorphous silicon layer may be deposited and then made into a single crystal by heat treatment such as laser annealing.

〔Effect of the invention〕

As described in detail above, according to the present invention, semiconductor devices such as high performance and highly reliable semiconductor memories that have excellent memory retention characteristics, stability of substrate potential, and excellent soft error resistance can be easily and easily manufactured. A method that can be mass-produced can be provided.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing a conventional epitaxial wafer, Figs. 2 to 4 show problems with conventional epitaxial wafers, and Fig. 2 shows a P ⁺ substrate -
An explanatory diagram showing the potential barrier between P-type single crystal silicon layers, Figure 3 is a schematic diagram to explain the movement of electrons generated in the single crystal silicon layer due to the incidence of alpha rays, and Figure 4 is a diagram showing the potential barrier between P-type single crystal silicon layers. FIG. 3 is a schematic diagram showing a state in which a capacitor electrode is provided. 5a to 5d are cross-sectional views showing the manufacturing process of the MOS dynamic RAM in Embodiment 1 of the present invention;
The figure is a cross-sectional view showing a modification of Example 1, and FIG.
c is a cross-sectional view showing the manufacturing process of the MOS dynamic RAM in Example 2 of the present invention, and FIGS. 8a to d
is the MOS dynamics in Embodiment 3 of the present invention.
Cross-sectional diagrams showing the manufacturing process of RAM, Figures 9 and 1
FIG. 0 is a sectional view showing other embodiments of the present invention. 11...P ⁺ type silicon substrate, 12, 12'...
P-type first single crystal silicon layer, 13... P-type second single crystal silicon layer, 14... Field oxide film, 15... Micro defect, 16... Capacitor electrode, 18... Transfer gate electrode, 22 ₁ ～
22 ₃ ...Al wiring, 24, 29...P-type single crystal silicon layer, 25...defect-free region, 26...Sapphire substrate, 27...P-type silicon substrate, 28...
…Oxide film.

Claims (1)

[Claims] On a single crystal semiconductor substrate of one conductivity type having a low specific resistance and containing impurities of 1 10 ¹⁷ /cm ³ or more, a first semiconductor substrate having a specific resistance higher than that of the substrate and of the same conductivity type as the substrate is provided. a step of epitaxially growing a single crystal semiconductor layer; a step of ion-implanting an impurity into the single crystal semiconductor layer; and a step of ion-implanting an impurity into the single crystal semiconductor layer; a step of epitaxially growing a second single crystal semiconductor layer, and performing heat treatment to form a large number of micro defects in the semiconductor substrate, and absorbing minority carriers into the first single crystal semiconductor layer into which the impurity ions have been implanted. 1. A method of manufacturing a semiconductor device, comprising: forming a large number of micro defects. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first single crystal semiconductor layer has a thickness of 1 to 3 μm.