JP2518378B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2518378B2 JP2518378B2 JP1030295A JP3029589A JP2518378B2 JP 2518378 B2 JP2518378 B2 JP 2518378B2 JP 1030295 A JP1030295 A JP 1030295A JP 3029589 A JP3029589 A JP 3029589A JP 2518378 B2 JP2518378 B2 JP 2518378B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- semiconductor device
- oxygen
- heat treatment
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特にシリコン
基板中の酸素の析出核による結晶欠陥をゲッタリング源
として用いる半導体装置の製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a crystal defect due to oxygen precipitation nuclei in a silicon substrate as a gettering source.
最近の高密度、高集積化した半導体装置の製造ではシ
リコン基板中の不純物を除去するために、何らかのゲッ
タリング方法を用いるのが一般的である。その中でシリ
コン基板中の酸素を析出核を利用するゲッタリング方法
をイントリンシックゲッタリング(以下IGという)と呼
ぶ。これはシリコン基板内部の結晶欠陥領域に半導体装
置の製造過程で潜入する汚染不純物をゲッタリングする
技術である。In recent manufacturing of high-density and highly integrated semiconductor devices, it is general to use some kind of gettering method to remove impurities in a silicon substrate. Among these, the gettering method that utilizes oxygen in the silicon substrate by utilizing precipitation nuclei is called intrinsic gettering (hereinafter referred to as IG). This is a technique for gettering contaminant impurities that infiltrate into a crystal defect region inside a silicon substrate during the manufacturing process of a semiconductor device.
意識的にIGを施す方法としては、長時間の高温熱処理
と長時間の低温熱処理を組み合せた方法が一般的であ
る。高温の熱処理はシリコン基板の表面付近の酸素をシ
リコン基板外に拡散放出(以下外方拡散という)するた
めであり、また低温熱処理はシリコン基板内部の欠陥核
を成長させるためのものである。高温熱処理による酸素
の外方拡散では、次の低温熱処理によりシリコン基板表
面に結晶欠陥発生の核となる酸素の析出がおきてはいけ
ないことから、シリコン基板表面の酸素濃度を酸素の固
溶度以下としなければならない。従って、この種の熱処
理をシリコン基板に施すと、シリコン基板の最表面では
酸素濃度は10-16乃至10-17原子/cm3(ASTM F−121−7
6による測定)となるのが一般的である。As a method of intentionally applying IG, a method combining a long-term high-temperature heat treatment and a long-term low-temperature heat treatment is generally used. The high temperature heat treatment is for diffusing and releasing oxygen near the surface of the silicon substrate out of the silicon substrate (hereinafter referred to as outward diffusion), and the low temperature heat treatment is for growing defect nuclei inside the silicon substrate. In the outward diffusion of oxygen by high-temperature heat treatment, the precipitation of oxygen, which is the nucleus of crystal defect generation, should not occur on the silicon substrate surface by the next low-temperature heat treatment, so the oxygen concentration on the silicon substrate surface should be less than the solid solubility of oxygen. And have to. Therefore, when this kind of heat treatment is applied to a silicon substrate, the oxygen concentration at the outermost surface of the silicon substrate is 10 -16 to 10 -17 atoms / cm 3 (ASTM F-121-7
6) is generally used.
また、意識せずとも半導体装置の製造過程において、
同様の現象が起こる。特にCMOS型半導体装置の製造プロ
セスでは、ウェル形成の高温熱処理によりシリコン基板
表面の酸素が外方拡散し、シリコン基板表面の酸素濃度
が低下する。In addition, in the process of manufacturing semiconductor devices,
A similar phenomenon occurs. Particularly in the manufacturing process of the CMOS type semiconductor device, the oxygen concentration on the surface of the silicon substrate is lowered due to the outward diffusion of oxygen on the surface of the silicon substrate due to the high temperature heat treatment for forming the well.
シリコン基板中の酸素は転位を固着しシリコン基板の
機械的強度をあげる働きがあるが、酸素濃度が1018原子
/cm3より低いとその働きが低下することが一般に知られ
ている。Oxygen in the silicon substrate has the function of fixing dislocations and increasing the mechanical strength of the silicon substrate, but the oxygen concentration is 10 18 atoms.
It is generally known that if it is lower than / cm 3 , its function is reduced.
上述した従来の半導体装置の製造方法では半導体素子
形成層であるシリコン基板表面の酸素濃度を低くするた
め、半導体装置を構成する物質である酸化シリコン膜や
窒化シリコン膜等の薄膜パターン端部での応力により、
シリコン基板表面に転位などの結晶欠陥が導入されやす
いという欠点がある。In the above-described conventional method for manufacturing a semiconductor device, in order to reduce the oxygen concentration on the surface of the silicon substrate that is the semiconductor element forming layer, the thin film pattern end portion such as a silicon oxide film or a silicon nitride film that is a substance forming the semiconductor device is formed. Due to stress
There is a drawback that crystal defects such as dislocations are easily introduced into the surface of the silicon substrate.
特に最近の高密度、高集積化した半導体装置において
は、薄膜パターンが複雑かつ微細となってきたため、パ
ターン端部での応力により転位等の結晶欠陥が導入され
やすい。Particularly in recent high-density and highly integrated semiconductor devices, the thin film pattern has become complicated and fine, so that crystal defects such as dislocations are likely to be introduced due to stress at the end of the pattern.
例えば、素子分離をフィールド酸化シリコン膜端部あ
るいは、ホットキャリヤ抑制の為のLDD(低濃度ドレイ
ン)構造トランジスタのゲート側壁材であるCVD法によ
る酸化シリコン膜端部での膜応力によるシリコン基板表
面に発生する転位等である。For example, element isolation is applied to the field silicon oxide film edge or the silicon substrate surface due to film stress at the silicon oxide film edge by the CVD method that is the gate sidewall material of the LDD (low-concentration drain) structure transistor for suppressing hot carriers. These are dislocations that occur.
これら結晶欠陥が導入された半導体装置では、半導体
素子の電気的特性の劣化を招き、その歩留り及び信頼性
の低下を引き起こすという欠点がある。The semiconductor device in which these crystal defects are introduced has a drawback that the electrical characteristics of the semiconductor element are deteriorated and the yield and reliability thereof are deteriorated.
本発明の目的は、IGの効果を十分保ちながらシリコン
基板表面の機械的強度をあげ、半導体素子の電気的特性
を向上させ、歩留り及び信頼性の高い半導体装置の製造
方法を提供することにある。An object of the present invention is to increase the mechanical strength of the surface of a silicon substrate while sufficiently maintaining the effect of IG, improve the electrical characteristics of semiconductor elements, and provide a method of manufacturing a semiconductor device with high yield and reliability. .
本発明の半導体装置の製造方法には、熱処理によりシ
リコン基板中に酸素を析出させてシリコン基板の内部に
結晶欠陥を導入する半導体装置の製造方法において、シ
リコン基板の内部に酸素の析出核を成長させ結晶欠陥を
導入した後、該シリコン基板表面に窒化シリコン膜を被
着し、次いでシリコン基板中の基板全体の酸素濃度の分
布を均一化するための熱処理を施すものである。According to the method of manufacturing a semiconductor device of the present invention, in a method of manufacturing a semiconductor device in which oxygen is precipitated in a silicon substrate by heat treatment to introduce crystal defects into the silicon substrate, oxygen precipitation nuclei are grown inside the silicon substrate. After introducing the crystal defects, a silicon nitride film is deposited on the surface of the silicon substrate, and then heat treatment is performed to make the oxygen concentration distribution in the entire silicon substrate uniform.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第1図は本発明の一実施例のシリコン基板中の酸素濃
度をSIMS(2次イオン質量分析)により測定したときの
深さ方向の分布図である。FIG. 1 is a distribution diagram in the depth direction when the oxygen concentration in the silicon substrate of one embodiment of the present invention is measured by SIMS (secondary ion mass spectrometry).
まず、1.8×1018原子/cm3の酸素を含むシリコン基板
を1200℃で3時間の熱処理を施し、シリコン基板表面付
近の酸素を外方拡散する。本処理によりシリコン基板表
面の酸素濃度は第1図の曲線L1で示すように1016原子/c
m3となる。次に、700℃4時間の熱処理を施し酸素濃度
が高いシリコン基板内部に酸素の析出核を成長させる。First, a silicon substrate containing 1.8 × 10 18 atoms / cm 3 of oxygen is subjected to heat treatment at 1200 ° C. for 3 hours to outwardly diffuse oxygen near the surface of the silicon substrate. By this treatment, the oxygen concentration on the surface of the silicon substrate is 10 16 atoms / c as shown by the curve L 1 in FIG.
the m 3. Next, heat treatment is performed at 700 ° C. for 4 hours to grow oxygen precipitation nuclei inside the silicon substrate having a high oxygen concentration.
この後、既知のLPCVD(減圧気相成長)法により、窒
化シリコン膜を厚さ50nmシリコン基板表面に被着し、酸
素雰囲気中1200℃で3時間の熱処理を施すと、シリコン
基板内部から表面へ酸素が拡散し第1図の曲線L2で示す
濃度となる。すなわち、シリコン基板表面の酸素濃度は
10/18原子/cm3となり、薄膜パターン端部の応力に対し
て十分な機械的強度を持たせることができる。Then, a known LPCVD (Low Pressure Vapor Deposition) method is used to deposit a silicon nitride film on the surface of a silicon substrate having a thickness of 50 nm, and heat treatment is performed at 1200 ° C. for 3 hours in an oxygen atmosphere. Oxygen diffuses to reach the concentration shown by the curve L 2 in FIG. That is, the oxygen concentration on the surface of the silicon substrate is
10/18 atoms / cm 3, and the can have a sufficient mechanical strength against stress of the thin film pattern end portion.
これらの処理を施した後、通常の選択酸化法によりフ
ィールド酸化シリコン膜を形成した試料の酸化シリコン
膜端部から発生した転位を選択エッチング法により観察
したところ、本実施例で作成したもので転位は全く観察
されなかった。一方、従来の方法で作成した試料には10
個/cm2の転位が観察された。なお、従来の方法はシリコ
ン基板表面の酸素濃度が1016原子/cm3となったままフィ
ールド酸化シリコン膜を形成したものである。After performing these treatments, the dislocation generated from the silicon oxide film end portion of the sample on which the field silicon oxide film was formed by the normal selective oxidation method was observed by the selective etching method. Was not observed at all. On the other hand, 10 for the sample prepared by the conventional method.
Dislocations of dislocations / cm 2 were observed. In the conventional method, the field silicon oxide film is formed with the oxygen concentration on the surface of the silicon substrate kept at 10 16 atoms / cm 3 .
以上のように本実施例によれば、フィールド酸化シリ
コン膜の端部からの転位は全く発生せず、シリコン基板
表面の機械的強度の劣化を防ぐことができる。従って、
この領域に設けられた半導体素子は電気的特性の劣化が
なく、高品質の半導体装置を高歩留りで得ることができ
る。As described above, according to this embodiment, no dislocation is generated from the end portion of the field silicon oxide film, and deterioration of the mechanical strength of the silicon substrate surface can be prevented. Therefore,
The semiconductor element provided in this region has no deterioration in electrical characteristics, and a high-quality semiconductor device can be obtained with high yield.
なお、窒化シリコン膜を直接シリコン基板表面に被着
する場合、被着条件によっては大きな歪が発生したシリ
コン基板表面に結晶欠陥が発生する場合がある。かかる
時はいったん酸化膜を10〜50nm被着した後に窒化シリコ
ン膜を設けると好ましい結果が得られる。When the silicon nitride film is directly deposited on the surface of the silicon substrate, a crystal defect may occur on the surface of the silicon substrate in which a large strain has occurred depending on the deposition conditions. In such a case, a desirable result can be obtained by once depositing an oxide film of 10 to 50 nm and then providing a silicon nitride film.
第2図は本発明のLDD構造のトランジスタで構成され
たCMOS型半導体装置に適用した場合の他の実施例な主な
工程における半導体チップの断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip in another main step of applying the invention to a CMOS type semiconductor device composed of an LDD structure transistor.
まず第2図(a)に示すように、N型シリコン基板1
の表面にホウ素をイオン注入した後、1150℃で熱処理す
ることによりPウェル2を形成し、その後選択的にフィ
ールドとなる酸化シリコン膜3を形成する。First, as shown in FIG. 2A, an N-type silicon substrate 1
After the boron is ion-implanted on the surface of the substrate, the P well 2 is formed by heat treatment at 1150 ° C., and then the silicon oxide film 3 to be a field is selectively formed.
次に第2図(b)に示すように、LPCVD法により窒化
シリコン膜4をシリコン基板1の表面に50nmの厚さに被
着する。その後、酸素雰囲気中で200℃,3時間の熱処理
を施すと、シリコン基板内部から表面へ酸素が拡散す
る。Next, as shown in FIG. 2 (b), a silicon nitride film 4 is deposited on the surface of the silicon substrate 1 to a thickness of 50 nm by the LPCVD method. Then, when heat treatment is performed at 200 ° C. for 3 hours in an oxygen atmosphere, oxygen diffuses from the inside of the silicon substrate to the surface.
次に第2図(c)に示すように、通常の方法によりMO
Sトランジスタのゲート5,CVD法により、ゲート側壁材で
ある酸化シリコン膜6,ソースドレイン7とを形成し、CM
OS型半導体装置を構造する。Next, as shown in FIG. 2 (c), MO
The gate 5 of the S transistor, the silicon oxide film 6 serving as the gate sidewall material, and the source / drain 7 are formed by the CVD method.
Structure an OS type semiconductor device.
第3図は横軸を逆バイアス電圧(V)、縦軸を逆方向
電流(A/cm2)とした場合の、CMOS型半導体装置のPN接
合の逆方向電圧電流特性を示す図である。図中、曲線A
は従来の方法により製造したCMOS型半導体装置の特性で
あり、曲線Bは本実施例の方法により製造した場合の特
性である。なお、この従来方法はフィールド酸化シリコ
ン膜を形成してただちにCMOS型半導体装置を製造する方
法であって、シリコン基板表面の酸素濃度が1016乃至10
17原子/cm3のものである。FIG. 3 is a diagram showing the reverse voltage-current characteristics of the PN junction of the CMOS type semiconductor device when the horizontal axis represents the reverse bias voltage (V) and the vertical axis represents the reverse current (A / cm 2 ). Curve A in the figure
Is the characteristic of the CMOS type semiconductor device manufactured by the conventional method, and the curve B is the characteristic when manufactured by the method of the present embodiment. It should be noted that this conventional method is a method of immediately manufacturing a CMOS semiconductor device by forming a field silicon oxide film, and the oxygen concentration on the surface of the silicon substrate is 10 16 to 10 16.
It is of 17 atoms / cm 3 .
第3図から明らかなように、従来例(曲線A)に比し
て本実施例(曲線B)においては、逆バイアスに対する
逆方向電流は極めて小さいことが分る。これは、従来の
方法ではシリコン基板表面の酸素濃度が低いため、トラ
ンジスタのゲート側壁材である酸化シリコン膜端部の応
力によりシリコン基板表面に転位が入ったためである。
内部欠陥が形成されているにもかかわらずIGの効果が現
れないのも、シリコン基板表面の転位が汚染不純物を捕
かくしているためである。As is apparent from FIG. 3, in this embodiment (curve B), the reverse current with respect to the reverse bias is extremely small compared to the conventional example (curve A). This is because the conventional method has a low oxygen concentration on the surface of the silicon substrate, so that dislocations are introduced into the surface of the silicon substrate due to the stress at the edges of the silicon oxide film that is the gate sidewall material of the transistor.
The reason why the IG effect does not appear despite the formation of internal defects is that dislocations on the surface of the silicon substrate trap contaminant impurities.
なお、曲線A,Bの測定結果が得られた試料表面の結晶
欠陥を選択エッチング法により観察したところ、本実施
例により作成した試料には5個/cm2の転位が観察された
が、従来方法により作成した試料には150個/cm2の転位
が観察された。When the crystal defects on the surface of the sample for which the measurement results of curves A and B were obtained were observed by the selective etching method, 5 dislocations / cm 2 were observed in the sample prepared according to this example. Dislocations of 150 dislocations / cm 2 were observed in the sample prepared by the method.
以上のように本実施例によれば、PN接合の逆方向電流
が減少し、高性能かつ高品質の半導体装置を高歩留りで
得ることができる。As described above, according to this embodiment, the reverse current of the PN junction is reduced, and a high-performance and high-quality semiconductor device can be obtained with a high yield.
以上説明したように本発明は、シリコン基板表面の無
欠陥層の酸素濃度を内部と同一にするために、酸素の析
出核により内部欠陥を導入した後、酸素が外方拡散しな
いように窒化シリコン膜をシリコン基板の表面に被着し
て熱処理を施し、内部に十分残存する酸素を基板表面に
まで拡散させる事により、シリコン基板表面での機械的
強度をあげることができると共に、薄膜等の応力によっ
てシリコン基板表面に導入される結晶欠陥を抑制できる
という効果がある。従って半導体素子の電気特性の劣化
がなく、歩留り及び信頼性の向上した半導体装置を得る
ことができる。As described above, according to the present invention, in order to make the oxygen concentration of the defect-free layer on the surface of the silicon substrate equal to that of the inside, after introducing internal defects by the precipitation nuclei of oxygen, silicon nitride is prevented from diffusing outward. By depositing the film on the surface of the silicon substrate and subjecting it to heat treatment to diffuse the oxygen remaining in the interior to the surface of the substrate, the mechanical strength on the surface of the silicon substrate can be increased and the stress of the thin film, etc. can be increased. This has the effect of suppressing the crystal defects introduced on the surface of the silicon substrate. Therefore, it is possible to obtain a semiconductor device with improved yield and reliability without deterioration of the electrical characteristics of the semiconductor element.
第1図は本発明の第一の実施例を説明するためのシリコ
ン基板中の酸素濃度の深さ方向の分布図、第2図は本発
明をLDD構造のトランジスタで構成されたCMOS型半導体
装置に適用した場合の主な工程における半導体チップの
断面図、第3図は実施例及び従来例におけるPN接合の逆
方向電圧電流特性を示す図である。 1……N型シリコン基板、2……Pウェル、3,6……酸
化シリコン膜、4……窒化シリコン膜、5……ゲート、
7……ソース・ドレイン。FIG. 1 is a distribution diagram of oxygen concentration in a silicon substrate in a depth direction for explaining the first embodiment of the present invention, and FIG. 2 is a CMOS type semiconductor device in which the present invention is composed of an LDD structure transistor. FIG. 3 is a cross-sectional view of a semiconductor chip in a main step when applied to FIG. 3, and FIG. 3 is a diagram showing reverse voltage-current characteristics of a PN junction in an example and a conventional example. 1 ... N-type silicon substrate, 2 ... P well, 3,6 ... silicon oxide film, 4 ... silicon nitride film, 5 ... gate,
7 ... Source / drain.
Claims (1)
させてシリコン基板の内部に結晶欠陥を導入する半導体
装置の製造方法において、シリコン基板の内部に酸素の
析出核を成長させ結晶欠陥を導入した後、該シリコン基
板表面に窒化シリコン膜を被着し、次いでシリコン基板
中の基板全体の酸素濃度の分布を均一化するための熱処
理を施すことを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device in which oxygen is precipitated in a silicon substrate by heat treatment to introduce crystal defects into the silicon substrate. In the method, oxygen precipitation nuclei are grown in the silicon substrate to introduce crystal defects. After that, a silicon nitride film is deposited on the surface of the silicon substrate, and then heat treatment is performed to make the oxygen concentration distribution of the entire substrate in the silicon substrate uniform.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030295A JP2518378B2 (en) | 1989-02-08 | 1989-02-08 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030295A JP2518378B2 (en) | 1989-02-08 | 1989-02-08 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02208940A JPH02208940A (en) | 1990-08-20 |
JP2518378B2 true JP2518378B2 (en) | 1996-07-24 |
Family
ID=12299745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1030295A Expired - Lifetime JP2518378B2 (en) | 1989-02-08 | 1989-02-08 | Method for manufacturing semiconductor device |
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Country | Link |
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JP (1) | JP2518378B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2606430B2 (en) * | 1990-10-01 | 1997-05-07 | 日本電気株式会社 | Semiconductor substrate |
US8426297B2 (en) | 2008-08-08 | 2013-04-23 | Sumco Techxiv Corporation | Method for manufacturing semiconductor wafer |
-
1989
- 1989-02-08 JP JP1030295A patent/JP2518378B2/en not_active Expired - Lifetime
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JPH02208940A (en) | 1990-08-20 |
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