JP3273037B2 - Method for manufacturing heterostructure semiconductor multilayer thin film - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a single crystal semiconductor thin film having a hetero structure, wherein a semiconductor having a composition different from that of a substrate semiconductor is laminated on a surface of a single crystal semiconductor substrate in one or more layers. Heterostructure single crystal semiconductor suitable for forming a semiconductor device by forming different heterogeneous semiconductors from high quality semiconductors with reduced crystal defects, and further forming another single crystal semiconductor containing strain thereon The present invention relates to a method for manufacturing a multilayer thin film.

[0002]

2. Description of the Related Art A conventional method for forming heterogeneous semiconductors having different compositions on a single crystal semiconductor substrate is described in, for example, Journal of Applied Physics, 1989, No. 65.
Vol. 2220 (Journal of Applied Physics, volume 65
(1989) p. 2220).

[0003]

In the above-described conventional heteroepitaxial growth method on a single crystal semiconductor, defects are generated inside the formed heterogeneous semiconductor. Therefore, when another single crystal semiconductor including a strain is further grown thereon, the strain is not sufficiently accumulated.

For example, when a field effect transistor is formed on a strained single crystal semiconductor, for example, the strain is not sufficiently accumulated, so that the effect that the strain is applied, the effective mass is reduced, and the carrier mobility increases is sufficiently achieved. Therefore, further improvement has been desired for increasing the speed of the semiconductor device.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to form a high-quality heterogeneous semiconductor with reduced crystal defects on a single-crystal semiconductor substrate, and to sufficiently form a strain thereon. It is an object of the present invention to provide a method for manufacturing a heterostructure single crystal semiconductor multilayer thin film, which enables formation of another accumulated single crystal semiconductor.

[0006]

Means for Solving the Problems In forming heterogeneous single crystal semiconductor layers having different compositions on a single crystal semiconductor substrate, the present inventors prevent generation of defects in the heterogeneous single crystal semiconductor layers. As a result of various experiments and investigations, important findings as described below have been obtained. The present invention has been made based on such findings.

That is, after a heterogeneous single crystal semiconductor layer having a different composition is formed on a single crystal semiconductor substrate, the lower layer portion is made amorphous by a predetermined thickness by ion implantation.
Thereafter, annealing is performed. Then, solid-phase growth proceeds unidirectionally using the vicinity of the surface of the heterogeneous single crystal semiconductor layer having relatively few crystal defects as a seed for recrystallization, and the crystallinity is improved.
However, in this case, since it is important that solid phase growth proceeds from near the surface, it is necessary to introduce an impurity for stopping solid phase growth at the interface between the single crystal semiconductor substrate and the heterogeneous single crystal semiconductor.

After the above steps are completed, only the upper layer portion of the heterogeneous single-crystal semiconductor layer is made amorphous by a predetermined thickness by ion implantation again, and then annealing is performed to improve the crystallinity. Solid phase growth is performed using the solid phase growth region as a seed for recrystallization. As a result, a heterogeneous single crystal semiconductor layer with good crystallinity is formed. Strain can be introduced into the single crystal semiconductor thin film by growing another single crystal semiconductor on the thus obtained heterocrystalline single crystal semiconductor layer having good crystallinity.

In the present invention, as described above, a heterogeneous semiconductor having many crystal defects formed by a normal method is once amorphized and then recrystallized to form a semiconductor heterostructure. . As a result, it is possible to form a semiconductor hetero multilayer structure in which distortion is sufficiently accumulated.

A typical method of manufacturing a heterostructure single crystal semiconductor thin film capable of achieving the above object of the present invention is characterized in that a heterogeneous single crystal semiconductor layer having a different composition from that of a single crystal semiconductor layer (first After the formation of the semiconductor layer), an impurity which inhibits solid phase growth is introduced into the interface between the two by using the first ion implantation method, and then the lower layer of the heterogeneous single crystal semiconductor layer (the first semiconductor layer) is formed. The portion is made amorphous by a predetermined thickness using a second ion implantation method, then annealed and recrystallized, and then an upper layer portion of the heterogeneous single crystal semiconductor layer is formed using a third ion implantation method. The point is that the film is made amorphous by a predetermined thickness, then annealed and then recrystallized. Thus, a high-quality heterogeneous semiconductor (first semiconductor layer) with reduced crystal defects can be formed over a single crystal semiconductor substrate.

In the present invention, a high-quality heterogeneous single-crystal semiconductor layer (first semiconductor layer) in which the crystal defects are further reduced.
Is used as a buffer layer, and a single crystal semiconductor thin film (second semiconductor layer) having a composition different from that of the heterogeneous single crystal semiconductor layer is grown thereon. Thereby, this single crystal semiconductor thin film (second
Strain can be sufficiently introduced into the semiconductor layer).

If a semiconductor device such as a field-effect transistor is formed on the second semiconductor layer, a carrier device having a higher carrier mobility than a conventional device, that is, a high-speed semiconductor device can be realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As the above semiconductor, for example, silicon is mentioned as a typical example, but it is not limited to this, and germanium and other commonly used semiconductor materials such as, for example, compound semiconductors such as gallium and arsenic are used. Can be used.

Here, a single crystal semiconductor substrate is a single crystal Si substrate, a heterogeneous single crystal semiconductor layer (first semiconductor layer) formed thereon is a SiGe mixed crystal, and a single crystal having a composition different from that of the heterogeneous single crystal semiconductor layer. An example in which the crystalline semiconductor thin film (second semiconductor layer) is made of single-crystal Si will be described.

An impurity which inhibits solid phase growth is introduced into an interface between a single crystal semiconductor (Si) substrate and a heterogeneous single crystal semiconductor layer (first semiconductor layer: SiGe mixed crystal) by using a first ion implantation method. In the step of forming the stopper layer by
As impurities that inhibit solid phase growth at the interface, for example, O ⁺ , N ⁺ ,
Irradiation with C ⁺ or the like may be performed by an ion implantation method. The ion implantation conditions are irradiation energy; 30 to 500 ke
V, dose: 10 ¹⁴ to 10 ¹⁶ cm ^-2 is preferable. From the viewpoint of efficiently reducing the amount of ion irradiation, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes to the interface. In this way, an impurity layer that inhibits solid phase growth is formed as a stopper layer at the interface.

Further, the lower layer portion of the heterogeneous single-crystal semiconductor layer (first semiconductor layer) is made amorphous by a predetermined thickness by a second ion implantation method, and then is annealed and recrystallized. Thereafter, the upper layer portion of the heterogeneous single crystal semiconductor layer is made amorphous by a predetermined thickness by using a third ion implantation method, and then is annealed and recrystallized to reduce crystal defects on the single crystal semiconductor substrate. The step of forming a high-quality heterogeneous semiconductor (first semiconductor layer: SiGe mixed crystal) will be specifically described below.

First, when amorphizing using the second ion implantation method, for example, Si ⁺ , Ge ⁺ ,
Irradiation energy of Ar ⁺ , Kr ^+, etc .; 30-500 keV,
Dose amount: 10 ¹⁴ to 10 ¹⁶ cm ^-2 is preferable. From the viewpoint of efficiently reducing the ion irradiation amount, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes near the lower region.

The subsequent annealing is performed at a temperature of 550 to 750.
° C., time 10 to 40 minutes, preferably carried out under conditions of ambient N ₂ gas, thereby making a single crystal of the made amorphous regions by ion implantation.

When the upper region is made amorphous by the third ion implantation method, an ion beam such as Si ⁺ , Ge ⁺ , Ar ⁺ , or Kr ⁺ is irradiated with an ion energy of 3;
0 to 500 keV, a dose amount; is 10 ¹⁴ ~10 ¹⁶ cm ^-2 preferred.
From the viewpoint of efficiently reducing the ion irradiation dose, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes near the upper region. That is, it is necessary to perform ion irradiation with lower energy than the first ion irradiation.

Thereafter, by performing the same annealing as that after the second ion implantation, the amorphous region can be made into a single crystal. In this manner, the first semiconductor layer (a mixed crystal of SiGe), which is a heterogeneous single crystal semiconductor layer, can be made of high quality with good crystallinity.

The high-quality first semiconductor layer (SiGe mixed crystal) thus obtained is used as a buffer layer thereon.
A single crystal semiconductor thin film having a different composition from this semiconductor layer (second semiconductor layer)
Is grown using, for example, an electron beam evaporation method. Thus, a single crystal semiconductor thin film (second semiconductor layer: Si film) in which distortion is sufficiently accumulated can be formed on the first semiconductor layer (SiGe mixed crystal) in which crystal defects are reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the drawings. <Embodiment 1> FIG. 1 is a sectional process view showing an example of a manufacturing method according to the present invention.

FIG. 1A shows a single crystal Si substrate 1. Fig. 1 (b)
Indicates a step of depositing a monocrystalline Si _1-X Ge _X layer (X ≦ 1.0) thereon. After the single crystal Si substrate 1 is chemically cleaned, it is introduced into a molecular beam growth apparatus, and after cleaning the surface, the single crystal Si _0.7 Ge _0.3 layer (thickness: 60
nm) 2 was deposited.

According to electron microscopic observation, single crystal Si _0.7 Ge _0.3
It was found that many crystal defects 3 remained at the interface between the layer and the single-crystal Si substrate, and the defect density decreased toward the surface side.

FIG. 1C shows the deposited monocrystalline Si _0.7 Ge _0.3 layer 2
Irradiation using an ion implantation method (energy; 30 to 500 keV, dose; 10 ¹⁴ to 10) at the interface between the substrate and the single crystal Si substrate 1 with impurities (O ⁺ , N ⁺ , C ^+, etc.) which inhibit solid phase growth. 10 ¹⁶ cm ^-2 )
This is the step of performing

That is, the stopper layer 4 which inhibits solid phase growth
Is a step of forming From the viewpoint of efficiently reducing the ion irradiation dose, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes to the interface. In this embodiment, as an example, O ⁺ ions are supplied at an energy of 25 keV to 10 ¹⁶ cm ^−2.
Irradiation was carried out for the dose amount.

FIG. 1D shows the deposited monocrystalline Si _0.7 Ge _0.3 layer 2
This is a step of amorphizing the lower region 5a of FIG. That is, Si
⁺ , Ge ⁺ , Ar ⁺ , Kr ^+, etc. ion energy (energy: 30 to 500 ke
V, a dose amount: 10 ¹⁴ to 10 ¹⁶ cm ^-2 ). From the viewpoint of efficiently reducing the ion irradiation amount, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes near the lower region.

In this embodiment, as an example, Si ⁺ ions are supplied at 50 keV.
It was irradiated by a dose of 10 ¹⁶ cm ^-2 at an energy. In this case, the peak position of the ion implantation distribution is
Located at a depth of 60 nm, its peak concentration is 1.5 × 10 ²¹ cm ^-3
It has become. Thus, the lower region 5a of the monocrystalline Si _0.7 Ge _0.3 layer 2 was made amorphous.

Next, the sample obtained by the above steps was
When annealing was performed at 0 ° C. for 15 minutes, solid phase growth proceeded from the surface side having relatively few crystal defects, and as a result, the above-mentioned amorphized region 5a was converted to high-quality monocrystalline Si _0.7 Ge _0.3 layer
Could be 6.

FIG. 1E shows a step of amorphizing the upper region 5b of the monocrystalline Si _0.7 Ge _0.3 layer 2. That is, Si ⁺ , Ge ⁺ , Ar
^This is a step of irradiating ion beams such as ⁺ , Kr ⁺ (energy; 30 to 500 keV, dose: 10 ¹⁴ to 10 ¹⁶ cm ^-2 ).

From the viewpoint of efficiently reducing the amount of ion irradiation, it is preferable to select the implantation energy so that the peak of the ion implantation distribution comes near the upper region. That is, it is necessary to perform ion irradiation with lower energy than the first ion irradiation.

After that, if annealing is performed, the region 6 with improved crystallinity in the first solid phase growth is used as a seed for crystal growth, and the upper amorphous region 5b is solid phase grown. As a result, high quality Si _0.7 Ge _0.3 layer 6 with good crystallinity (buffer layer)
Was formed. In this embodiment, as an example, annealing is performed at 600 ° C. for 15 minutes. The results are shown in FIG.

FIG. 1 (g) shows that on a high quality Si _0.7 Ge _0.3 layer 6,
Single-crystal Si layer (thickness: 450 ° C.) using electron beam evaporation
This is the step of growing (20 nm) 6. Observation with an electron microscope after crystal growth revealed that the single crystal Si layer 7 and single crystal Si _0.7 Ge
_No defect was observed at the interface with _0.3 layer 6.

FIG. 2 shows the results of calculating the value of the strain introduced into the monocrystalline Si layer 7 using Raman spectroscopy. The solid line in the figure is the measurement result of the sample prepared according to the present invention, that is, FIGS.
It is a measurement result of the sample created in the step of FIG.

On the other hand, the dotted line shows the measurement results of the comparative sample prepared by the conventional method, that is, directly on the monocrystalline Si _0.7 Ge _0.3 layer 2 prepared in the steps of FIGS. 1 (a) and 1 (b). FIG. 1 (f) shows the measurement results of a sample in which a single-crystal Si layer (thickness: 20 nm) 7 was grown at 450 ° C. using the electron beam evaporation method.

The value of the solid line in this embodiment is much higher than the value of the comparative example in the dotted line. In contrast to the conventional method in which the strain is relaxed due to the remaining crystal defects, the method of the present invention requires more strain than the conventional method in order to form a semiconductor hetero multilayer structure having no crystal defects. Is made possible.

<Embodiment 2> FIG. 3 is a cross-sectional view of a field effect transistor prototyped using the present invention. In Prototype Example A, a normal thermal oxidation process was performed on the strained single-crystal Si layer 7 formed on the single-crystal Si substrate 1 according to the procedure described in Embodiment 1 to obtain a single-crystal Si substrate.
A gate oxide film 8 having a thickness of 36 nm was formed.

In the prototype B, the strained single crystal prepared by the conventional method was used.
1 directly on the Si layer 7, that is, the monocrystalline Si _0.7 Ge _0.3 layer 2 (buffer layer) formed in the steps of FIGS. 1 (a) and 1 (b).
Step (f), i.e., a 136 nm thick gate oxide using a normal thermal oxidation step on a sample on which a monocrystalline Si layer (thickness: 20 nm) 7 was grown at 450 ° C. using an electron beam evaporation method. The film 8 was formed.

In the prototype C, a 136 nm thick gate oxide film 8 was formed on the single crystal Si substrate 1 by using a normal thermal oxidation process.

Thereafter, after forming a polycrystalline Si gate 9 by a usual photolithography technique for any of the samples, the oxide film 8 is partially removed, and then approximately 1 × 10 ²⁰ cm ^-3 is formed by ion implantation. N ⁺ -layers 10, 11 containing about phosphorus atoms
Was formed. That is, each is the source 10 and the drain 11 of the transistor. Finally, photolithography and Al
A source / drain electrode and a gate electrode were formed by using the vapor deposition method described above to complete a field effect transistor.

As a result of measuring the characteristics of these transistors, normal transistor operation was confirmed in all prototypes. The mobility of the obtained carrier is shown in prototype A (this embodiment).
Was 1000 cm ² / Vs, whereas the prototype B (comparative example 1) was 700 cm ² / Vs, and the prototype C (comparative example 2) was 500 cm ² / Vs.
cm ² / Vs.

That is, in the prototype C (comparative example 2), the single-crystal Si
As compared with the case where the normal mobility of the layer is observed, in the prototypes A (this example) and B (comparative example 1), the strain is applied and the effective mass is reduced, so that the carrier mobility is increased. Is observed.

In this case, in the prototype B, the distortion is relaxed due to the remaining crystal defects, whereas in the prototype A, a semiconductor hetero multilayer structure with reduced crystal defects is formed. It is possible to introduce more strain than in Example B, and to reduce the effective mass and increase the mobility.

[0044]

As described above in detail, according to the present invention, it is possible to form a semiconductor hetero-multilayer structure having few crystal defects and accumulated strain. As a result, a high-quality semiconductor hetero-multilayer structure that could not be obtained by the conventional technology was easily realized. This invention opens a new way to realize next-generation electronics.

[Brief description of the drawings]

FIG. 1 is a cross-sectional process diagram showing a process of forming a semiconductor hetero multilayer structure on a single crystal Si substrate according to one embodiment of the present invention.

FIG. 2 is a characteristic diagram comparing an example of the present invention and a conventional example with respect to a value of strain introduced into a semiconductor hetero multilayer structure.

FIG. 3 is a cross-sectional view of a semiconductor device in which a field-effect transistor is formed using a heterostructure single crystal semiconductor thin film according to one embodiment of the present invention.

[Explanation of symbols]

1 ... Single-crystal Si substrate, 2 ... Single-crystalline Si _0.7 Ge _0.3 layer, 3 ... Crystal defect, 4 ... Stopper layer of solid phase growth, 5a ... First amorphous region generated by ion implantation, 5b ... Ion Second amorphous region generated by implantation, 6 ... High quality Si _0.7 Ge _0.3 layer recrystallized by solid phase epitaxy, 7 ... Strained single crystal Si, 8 ... Gate oxide film, 9 ... Gate, 10 ... source, 11 ... drain.

Continuation of the front page (72) Inventor Shinya Yamaguchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-246619 (JP, A) (58) Fields investigated ( Int.Cl. ⁷ , DB name) H01L 21/20

Claims (7)

(57) [Claims] An impurity which inhibits solid phase growth is introduced into an interface between a single crystal semiconductor layer having a different composition from that of a single crystal semiconductor layer formed on the single crystal semiconductor substrate by using a first ion implantation method. A stopper layer is formed, and then the lower layer portion of the heterogeneous single-crystal semiconductor layer is made amorphous by a predetermined thickness using a second ion implantation method, and then is annealed and recrystallized. The upper layer portion of the heterogeneous single crystal semiconductor layer is made amorphous by a predetermined thickness by using the ion implantation method, and then annealed and recrystallized to form a heterogeneous single crystal semiconductor layer with reduced crystal defects. A method for producing a heterostructure single crystal semiconductor thin film, characterized in that: 2. After forming a first heterogeneous single-crystal semiconductor layer having a composition different from that of a single-crystal semiconductor substrate on a single-crystal semiconductor substrate, an impurity which inhibits solid-phase growth at the interface between the two by using a first ion implantation method. Then, a stopper layer is formed, and thereafter, a lower layer portion of the first heterogeneous single-crystal semiconductor layer is made amorphous by a predetermined thickness by a second ion implantation method. After that, the upper layer portion of the first heterogeneous single crystal semiconductor layer was made amorphous by a predetermined thickness by using a third ion implantation method, and then annealed and recrystallized to reduce crystal defects. A first heterogeneous single-crystal semiconductor layer; a recrystallized first heterogeneous single-crystal semiconductor layer as a buffer layer; and a second single-crystal semiconductor layer having a composition different from that of the first heterogeneous single-crystal semiconductor layer. Crystal growth of crystalline semiconductor thin film, A method for producing a heterostructure single-crystal semiconductor multilayer thin film, characterized by introducing strain into the single-crystal semiconductor thin film. 3. The single-crystal semiconductor substrate is Si, the first hetero-single-crystal semiconductor formed thereon is Si _1-X Ge _X , and the second single-crystal semiconductor formed thereon is strained. Thin film
3. The method for producing a heterostructure single-crystal semiconductor multilayer thin film according to claim 1, wherein the thin film is Si. 4. When forming a stopper layer by introducing an impurity that inhibits solid phase growth into the interface between the two by using the first ion implantation method, O ⁺ , N ⁺ , or C ⁺ is used as an impurity. Irradiation energy 30 to 500 keV, dose 10 ¹⁴ to 10
3. The method according to claim 1, wherein the ion implantation is performed under the condition of ¹⁶ cm.sup.- ² , and the implantation energy is selected so that the peak of the ion implantation distribution comes to the interface. Method. 5. In amorphized to using the second ion implantation ^{method, Si +, Ge +, Ar} +, or Kr ⁺ irradiation energy 30 to 500 keV ion beam as the ion species, dose ion-implanted under conditions of an amount 10 ¹⁴ ~10 ¹⁶ cm ^-2, and claim 1 or 2, wherein the heterostructure single, characterized in that selecting the energy implantation to come a peak of ion implantation distribution in the vicinity of the lower region A method for producing a crystalline semiconductor multilayer thin film. 6. When the upper region is made amorphous by the third ion implantation method, Si ⁺ , Ge is used as an ion species.
⁺ , Ar ⁺ , or Kr ⁺ ion beam irradiation energy 30 to 500
keV, and ion implantation with a dose of 10 ¹⁴ ~10 ¹⁶ cm ^-2, and, according to claim 1 or 2, wherein the selecting the implantation energy such that the peak of the ion implantation distribution in the vicinity of the upper region comes A method for manufacturing a heterostructure single crystal semiconductor multilayer thin film. 7. The annealing after the second and third ion implantations is performed at a temperature of 550 to 750 ° C., respectively.
3. The method according to claim 1, wherein the step is performed for 0 to 40 minutes.
The method for producing a heterostructure single crystal semiconductor multilayer thin film according to the above.