JP2936878B2 - Manufacturing method of semiconductor Schottky junction - Google Patents

Manufacturing method of semiconductor Schottky junction

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Publication number
JP2936878B2
JP2936878B2 JP6908892A JP6908892A JP2936878B2 JP 2936878 B2 JP2936878 B2 JP 2936878B2 JP 6908892 A JP6908892 A JP 6908892A JP 6908892 A JP6908892 A JP 6908892A JP 2936878 B2 JP2936878 B2 JP 2936878B2
Authority
JP
Japan
Prior art keywords
molecular beam
schottky junction
gaas
semiconductor schottky
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6908892A
Other languages
Japanese (ja)
Other versions
JPH05226640A (en
Inventor
信次 藤枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP6908892A priority Critical patent/JP2936878B2/en
Publication of JPH05226640A publication Critical patent/JPH05226640A/en
Application granted granted Critical
Publication of JP2936878B2 publication Critical patent/JP2936878B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、GaAsに金属を積層
したショットキー接合を有する半導体デバイスおよびそ
の作製方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a Schottky junction formed by laminating a metal on GaAs and a method of manufacturing the same.

【0002】[0002]

【従来の技術】GaAsのショットキー接合は、金属−
半導体接合型電界トランジスタ−(MESFET)等、
電子デバイスのゲートを構成する要素として重要であ
る。ショットキー接合の主要な性能指標は、障壁高さ
(Schottky barrier height,
SBH)であり、従来、SBHは、積層する金属の種類
によって制御されていた。
2. Description of the Related Art A Schottky junction of GaAs is made of metal-
Semiconductor junction type electric field transistor-(MESFET), etc.
It is important as an element constituting a gate of an electronic device. The main performance index of the Schottky junction is Schottky barrier height,
SBH), and conventionally, SBH has been controlled by the type of metal to be laminated.

【0003】[0003]

【発明が解決しようとする課題】上記トランジスターの
動作特性向上には高いSBHが望まれるが、SBHは、
金属の種類で決まってしまうので、金属種の選択範囲が
限定されるという問題がある。
A high SBH is desired to improve the operation characteristics of the above-mentioned transistor.
Since it is determined by the type of metal, there is a problem that the selection range of the metal type is limited.

【0004】本発明の目的は、金属種によらずに高いS
BHを実現する半導体ショットキー接合およびその作製
方法を提供することにある。
It is an object of the present invention to achieve a high S
An object of the present invention is to provide a semiconductor Schottky junction realizing BH and a method for manufacturing the same.

【0005】[0005]

【0006】[0006]

【課題を解決するための手段】 前記目的を達成するた
め、 本発明に係る半導体ショットキー接合の作製方法
は、基板上に中間層を形成し、次いで金属を積層する半
導体ショットキー接合の作製方法であって、中間層形成
工程は、基板温度250℃以下において、As分子線と
Ga分子線を用い、As/Ga分子線フラックス比を堆
積する膜がアモルファスにならない範囲で可能な限り小
さく設定して、GaAs層を成長させたのち、試料をお
よそ450〜550℃の温度範囲内でAs分子線を照射
せずに熱処理を行う工程である。
In order to achieve the above object,
Therefore, the method for producing a semiconductor Schottky junction according to the present invention is a method for producing a semiconductor Schottky junction in which an intermediate layer is formed on a substrate, and then a metal is laminated. In the following, after using an As molecular beam and a Ga molecular beam and setting the As / Ga molecular beam flux ratio to be as small as possible within a range where the deposited film does not become amorphous, a GaAs layer is grown. This is a step of performing a heat treatment within a temperature range of 5550 ° C. without irradiating an As molecular beam.

【0007】[0007]

【作用】本発明は、GaAs上に形成した極めて薄いG
aの過剰なGaAs膜に含まれる深い準位によってSB
Hを制御するものである。
According to the present invention, an extremely thin G layer formed on GaAs is formed.
a due to the deep levels contained in the excess GaAs film
H is controlled.

【0008】Gaの過剰なGaAs膜、すなわち組成比
(GaとAs原子数比率)が1以下である膜には、As
サイトにGaが置かれたアンチサイト欠陥が多く含まれ
る。Gaアンチサイト欠陥の作る深い準位に表面ポテン
シャルを固定させることにより、金属種に依存しない高
いSBHが得られる。GaAs中のGaアンチサイト欠
陥は、伝導帯の下1電子ボルト(eV)に準位をつくる
ので、n型GaAs上に、Gaの過剰なGaAsの中間
層を形成することにより、およそ1eVという高いSB
Hが得られる。
A GaAs film having an excessive amount of Ga, that is, a film having a composition ratio (ratio of Ga to As atoms) of 1 or less, contains As
Many anti-site defects in which Ga is placed on the site are included. By fixing the surface potential to the deep level created by the Ga antisite defect, a high SBH independent of the metal species can be obtained. Since Ga antisite defects in GaAs create a level one electron volt (eV) below the conduction band, the formation of a Ga-rich GaAs intermediate layer on n-type GaAs results in a high level of about 1 eV. SB
H is obtained.

【0009】Gaの過剰なGaAs膜を作製する信頼性
の高い方法として、請求項2に述べた方法を開発した。
すなわち、MBE法により構造を形成する際、As/G
a分子線フラックス比は、本発明の中間層作製には極力
抑制すべきであるが、基板温度が高いと、Gaの液滴が
生じやすく、平坦な表面が得られないので基板温度を2
50℃以下にする。
As a highly reliable method for producing a GaAs film containing excess Ga, a method described in claim 2 has been developed.
That is, when forming a structure by the MBE method, As / G
a The molecular beam flux ratio should be suppressed as much as possible for the production of the intermediate layer of the present invention. However, if the substrate temperature is high, Ga droplets are likely to be generated, and a flat surface cannot be obtained.
Keep below 50 ° C.

【0010】この温度範囲では、As/Ga分子線フラ
ックス比が小さすぎると、膜がアモルファスになる。こ
のアモルファスGaAsは、後工程の熱処理によって結
晶化するが、これにはGaアンチサイト欠陥以外に、浅
い準位をつくるAs空孔等の欠陥が含まれるので不都合
である。
In this temperature range, if the As / Ga molecular beam flux ratio is too small, the film becomes amorphous. This amorphous GaAs is crystallized by a heat treatment in a later step, but is disadvantageous because it includes defects such as As vacancies that form shallow levels in addition to Ga antisite defects.

【0011】As/Ga分子線フラックス比を堆積する
膜がアモルファスにならない範囲で可能な限り小さく設
定し、堆積膜を上記温度範囲で熱処理することにより、
主としてGaアンチサイト欠陥のみを含むGaAsが得
られる。
The As / Ga molecular beam flux ratio is set as small as possible within a range where the deposited film does not become amorphous, and the deposited film is heat-treated in the above temperature range.
GaAs mainly containing only Ga antisite defects is obtained.

【0012】[0012]

【実施例】以下に本発明の実施例を説明する。化学エッ
チングを施したSiドープn(プラス)(100)Ga
As基板をMBE装置内に導入した。1×10-5Tor
rのAs分子線を照射しながら基板を630℃まで昇温
し、表面の酸化膜を蒸発させた。続けて620℃でG
a,Si分子線も加えて照射し、n型GaAs層を成長
させた。
Embodiments of the present invention will be described below. Chemically etched Si-doped n (plus) (100) Ga
The As substrate was introduced into the MBE device. 1 × 10 -5 Torr
The substrate was heated to 630 ° C. while irradiating r As molecular beam, and the oxide film on the surface was evaporated. Continue G at 620 ° C
Irradiation was also performed by adding a and Si molecular beams to grow an n-type GaAs layer.

【0013】この後、As分子線照射を続けながら、基
板温度を200℃に下げた。強度を1×10−6Tor
rに下げたAs分子線と、Ga分子線とにより厚さ2ナ
ノメーター(nm)のGaAs中間層を速度0.22n
m/秒で形成した。この成長条件は、As/Gaフラッ
クス比0.6に相当する。
Thereafter, the substrate temperature was lowered to 200 ° C. while continuing the As molecular beam irradiation. Strength 1 × 10 −6 Torr
The GaAs intermediate layer having a thickness of 2 nanometers (nm) is formed at a speed of 0.22 n by the As molecular beam reduced to r and the Ga molecular beam.
m / sec. This growth condition depends on the As / Ga flash
The ratio of 0.6.

【0014】最後に、すべての分子線を止め、試料を4
90℃で10分間熱処理した。MBE装置から取り出し
た試料上に金およびアルミニウムの電極を通常のリソグ
ラフィーにより形成し、ショットキー接合とした。
Finally, all the molecular beams are stopped, and the sample is
Heat treatment was performed at 90 ° C. for 10 minutes. Gold and aluminum electrodes were formed on the sample taken out of the MBE apparatus by ordinary lithography, and a Schottky junction was formed.

【0015】電流−電圧特性から求めたSBHは、金で
0.96eV,アルミニウムでも0.94eVであり、
通常値(それぞれ0.84eV,0.63eV)より高
くなった。GaAs中間層成長速度を0.22nm/秒
に固定した場合、アルミニウムのSBHは、As分子線
強度が1×10-5Torrと高い時には0.54eVに
減少し、膜がアモルファスになる5×10-7Torrで
も0.84eVに減少した。
The SBH determined from the current-voltage characteristics is 0.96 eV for gold and 0.94 eV for aluminum.
The values were higher than normal values (0.84 eV and 0.63 eV, respectively). When the GaAs intermediate layer growth rate is fixed at 0.22 nm / sec, the SBH of aluminum decreases to 0.54 eV when the As molecular beam intensity is as high as 1 × 10 −5 Torr, and the film becomes amorphous 5 × 10 5 Even at -7 Torr, it decreased to 0.84 eV.

【0016】[0016]

【発明の効果】本発明によれば、金属種によらずに高い
SBHを実現することができ、デバイス構造・プロセス
の設計の自由度が増すとともに、デバイス性能の向上を
図ることができる。
According to the present invention, a high SBH can be realized irrespective of the type of metal, and the degree of freedom in designing the device structure and process can be increased, and the device performance can be improved.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板上に中間層を形成し、次いで金属を
積層する半導体ショットキー接合の作製方法であって、 中間層形成工程は、基板温度250℃以下において、A
s分子線とGa分子線を用い、As/Ga分子線フラッ
クス比を堆積する膜がアモルファスにならない範囲で可
能な限り小さく設定して、GaAs層を成長させたの
ち、試料をおよそ450〜550℃の温度範囲内でAs
分子線を照射せずに熱処理を行う工程であることを特徴
とする半導体ショットキー接合の作製方法。
1. A method for producing a semiconductor Schottky junction in which an intermediate layer is formed on a substrate and then a metal is laminated, wherein the step of forming the intermediate layer comprises the steps of:
After growing a GaAs layer by using an s molecular beam and a Ga molecular beam and setting the As / Ga molecular beam flux ratio as small as possible within a range where the deposited film does not become amorphous, the sample is heated to about 450 to 550 ° C. Within the temperature range of
A method for producing a semiconductor Schottky junction, which is a step of performing a heat treatment without irradiating a molecular beam.
JP6908892A 1992-02-18 1992-02-18 Manufacturing method of semiconductor Schottky junction Expired - Lifetime JP2936878B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6908892A JP2936878B2 (en) 1992-02-18 1992-02-18 Manufacturing method of semiconductor Schottky junction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6908892A JP2936878B2 (en) 1992-02-18 1992-02-18 Manufacturing method of semiconductor Schottky junction

Publications (2)

Publication Number Publication Date
JPH05226640A JPH05226640A (en) 1993-09-03
JP2936878B2 true JP2936878B2 (en) 1999-08-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2936878B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5898210A (en) * 1996-06-14 1999-04-27 The United States Of America As Represented By The Secretary Of The Army Semiconductor diode with high turn on and breakdown voltages
JP5010129B2 (en) * 2005-09-30 2012-08-29 株式会社東芝 Light emitting diode and manufacturing method thereof
JP2010225981A (en) * 2009-03-25 2010-10-07 Fujitsu Ltd Optical semiconductor device, integrated element and method of manufacturing optical semiconductor device

Also Published As

Publication number Publication date
JPH05226640A (en) 1993-09-03

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