JPH0787179B2 - Method for manufacturing superlattice semiconductor device - Google Patents

Method for manufacturing superlattice semiconductor device

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Publication number
JPH0787179B2
JPH0787179B2 JP59153968A JP15396884A JPH0787179B2 JP H0787179 B2 JPH0787179 B2 JP H0787179B2 JP 59153968 A JP59153968 A JP 59153968A JP 15396884 A JP15396884 A JP 15396884A JP H0787179 B2 JPH0787179 B2 JP H0787179B2
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Prior art keywords
group
iii
semiconductor
compound
crystal substrate
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JPS6134922A (en
Inventor
潤一 西澤
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新技術事業団
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Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は自己停止機能を有した分子層単位の超格子を有
する半導体装置の製造方法に関する。
TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a superlattice of a molecular layer unit having a self-stop function.

〔先行技術と問題点〕[Prior art and problems]

半導体単体では得られない特性の実現のために、異なる
半導体を周期的に形成したものとして超格子構造の半導
体装置が知られている。しかし、この超格子構造の半導
体装置は、結晶の一次元方向に、母結晶の格子定数に比
べて十分長く、電子の平均自由行程よりは短かい周期的
ポテンシャルを設けた構造としなければならないことか
ら、製造が難かしく、現在までのところ製造は実験段階
に止り工業化に至っていない。というのは、半導体の製
造法として従来より分子線エピタキシャル法(以下、MB
E法と略す)、有機金属による結晶成長法(以下、MO−C
VD法と略す)原子層エピタキシャル法(以下、ALEと略
す)等が知られているが、いずれも膜厚制御性や結晶性
が悪く超格子構造とするのは容易ではないもしくは形成
できないからである。即ち、MBE法の場合は、分子線ソ
ースを基板に当てて成長を行なうために化学量論的組成
(ストイキオメトリー)を完全には満しにくいこと、基
板に吸着した原子が液相成長のようには結晶表面を自由
に動きまわらないことから良好な結晶構造が得られない
欠点があった。
A semiconductor device having a superlattice structure is known as one in which different semiconductors are periodically formed in order to realize characteristics that cannot be obtained by a single semiconductor. However, this superlattice structure semiconductor device must have a structure in which a periodic potential is provided in the one-dimensional direction of the crystal that is sufficiently longer than the lattice constant of the host crystal and shorter than the mean free path of electrons. Therefore, it is difficult to manufacture, and so far, the manufacturing has stopped at the experimental stage and has not been industrialized. This is because the molecular beam epitaxial method (hereinafter referred to as MB
Abbreviated as E method), crystal growth method using organic metal (hereinafter MO-C
Atomic layer epitaxial method (abbreviated as VD method) (hereinafter abbreviated as ALE) and the like are known, but in both cases, it is not easy to form a superlattice structure because of poor film thickness controllability and crystallinity. is there. In other words, in the case of the MBE method, it is difficult to completely satisfy the stoichiometric composition (stoichiometry) because the molecular beam source is applied to the substrate for growth, and the atoms adsorbed on the substrate do not undergo liquid phase growth. As described above, since the crystal surface does not move freely, there is a drawback that a good crystal structure cannot be obtained.

MO−CVD法では、Japan.J.Appl.Phys.19,(1980)L551〜
L554等に超格子構造の形成例が示されているが、異なる
半導体相互の境界層(遷移層)の厚みが60Å(約29分子
層)と示されているように分子層単位の精度での成長膜
厚の制御が困難なこと、600℃といった高温の基板温度
が要求されること、熱分解反応によることからもともと
結晶性が悪いという欠点があった。ALE法は特開昭55−1
30896号公報に示されるように化合物半導体の成分元素
を含む蒸気をガラス基板表面に交互に導入し、交換表面
反応により薄膜を形成するものであるが、多結晶やアモ
ルファスであるため格子定数が定義されず、超格子構造
を形成できない欠点があった。またALE法では蒸気交互
導入1サイクルで1/3分子層以下しか成長できない欠点
があった。さらにALE法ではIII−V族化合物半導体やSi
が成長できないというような欠点を有していた。
In the MO-CVD method, Japan.J.Appl.Phys.19, (1980) L551 ~
An example of forming a superlattice structure is shown in L554, etc., but as the thickness of the boundary layer (transition layer) between different semiconductors is shown to be 60Å (about 29 molecular layers), it is It has the drawbacks that the crystallinity is originally poor because it is difficult to control the grown film thickness, a high substrate temperature of 600 ° C is required, and because of the thermal decomposition reaction. The ALE method is disclosed in JP-A-55-1.
As shown in Japanese Patent No. 30896, vapors containing component elements of a compound semiconductor are alternately introduced to the surface of a glass substrate to form a thin film by an exchange surface reaction, but the lattice constant is defined because it is polycrystalline or amorphous. Therefore, there is a drawback that a superlattice structure cannot be formed. In addition, the ALE method has a drawback that only one-third molecular layer or less can grow in one cycle of alternate steam introduction. Furthermore, in the ALE method, III-V compound semiconductors and Si
Had the drawback that it could not grow.

〔発明の目的〕[Object of the Invention]

本発明は上記の点に鑑み、新規な方法により超格子構造
の半導体装置を工業的に分子層単位で精密に製造できる
方法を提供することを目的とする。
In view of the above points, an object of the present invention is to provide a method for industrially precisely manufacturing a semiconductor device having a superlattice structure on a molecular layer basis by a novel method.

〔発明の概要〕[Outline of Invention]

本発明は真空に排気する成長槽内に外部より結晶成分元
素を含むガスを所定の条件で交互に導入することによ
り、ガス導入1サイクルで少なくとも1分子層形成し成
長膜厚を分子層単位で制御し、化学量論的組成を満たす
結晶を成長させることにより、分子層数で設計可能な超
格子半導体装置が得られるようにしたことを特徴として
いる。
According to the present invention, at least one molecular layer is formed in one cycle of gas introduction by alternately introducing a gas containing a crystal component element from the outside into a growth tank that is evacuated to a vacuum, and the growth film thickness is measured in molecular layer units. It is characterized in that a superlattice semiconductor device which can be designed by the number of molecular layers can be obtained by controlling and growing a crystal satisfying the stoichiometric composition.

〔発明の実施例〕 以下、本発明の実施例をGaAs−Ga1-xAlxAs1-yPyの超格
子半導体装置を製造する場合を例にとり説明する。
EXAMPLE OF THE INVENTION In the following, will be described taking as an example a case of manufacturing a superlattice semiconductor device of GaAs-Ga 1-x Al x As 1-y P y an embodiment of the present invention.

第1図は本発明の一実施例に係る結晶成長装置の構成図
を示したものである。図において、1は成長槽で材質は
ステンレス等の金属、2はゲートバルブ、3は成長槽1
を超高真空に排気するための排気装置、4はGaCl3また
はTMG(トリメチルガリウム)等のGaを含む化合物ガス
を導入するノズル、5はAsH3等のAsを含む化合物ガスを
導入するノズル、6はTMA(トリメチルアルミニウム)
等のAlを含む化合物ガスを導入するノズル、7はPH3、P
Cl3等のPを含む化合物ガスを導入するノズル、8,9,10,
11は前記ノズルを開閉するバルブで、ガス源12(GaCl3
等)、13(AsH3)、14(TMA等)、15(PH3等)との間に
設けられたもの、16は基板加熱用のヒーターで石英ガラ
スに封入したタングステン(W)線で配線は図示省略し
ているもの、17は測温用の熱電対、18はGaAs基板で、ノ
ズル4,5,6,7の先端開孔部はGaAs基板表面方向を向き、
しかも基板表面にできるだけ近づけて配置されている。
19は成長槽内の圧力を測定するための圧力計である。
FIG. 1 is a block diagram of a crystal growth apparatus according to an embodiment of the present invention. In the figure, 1 is a growth tank, the material is metal such as stainless steel, 2 is a gate valve, 3 is a growth tank 1
To an ultra-high vacuum, 4 is a nozzle for introducing a compound gas containing Ga such as GaCl 3 or TMG (trimethylgallium), 5 is a nozzle for introducing a compound gas containing As such as AsH 3 , 6 is TMA (trimethylaluminum)
Such as a nozzle for introducing a compound gas containing Al, 7 is PH 3 , P
Nozzle for introducing a compound gas containing P such as Cl 3 , 8, 9, 10,
11 is a valve that opens and closes the nozzle, and is a gas source 12 (GaCl 3
Etc.), 13 (AsH 3 ), 14 (TMA etc.), 15 (PH 3 etc.), 16 is a heater for heating the substrate and is a tungsten (W) wire enclosed in quartz glass Are not shown in the figure, 17 is a thermocouple for temperature measurement, 18 is a GaAs substrate, and the tip openings of the nozzles 4, 5, 6 and 7 face the surface of the GaAs substrate,
Moreover, they are arranged as close to the substrate surface as possible.
Reference numeral 19 is a pressure gauge for measuring the pressure in the growth tank.

この構成で、GaAs基板18上にGaAsをエピタキシャル成長
させる場合は、先ず、ゲートバルブ2を開け、超高真空
排気装置3により成長槽1内を10-7〜10-8Pascal(以
下、Paと略す)程度に排気する。次に、GaAs基板18を30
0〜800℃望ましくは300〜500℃にヒーター16により加熱
した後に、TMG12を成長槽1内の圧力が10-1〜107Paとな
る範囲で1分子層形成に必要な分子数よりも十分多く0.
5〜10秒間バルブ8を開けて導入し、1分子吸着層を形
成する。次に、1分子吸着層形成に余った余分のTMGを
成長槽1内より排気後、AsH313を成長槽1内の圧力が10
-1〜107Paとなる範囲で1分子吸着層形成に必要な分子
数よりも十分多く2〜200秒間バルブ5を開けて導入す
る。1分子吸着層形成に余った余分のAsH313はその後排
気する。このガス導入1サイクルに伴う交換表面反応で
GaAs1分子層が自己停止機能を有して成長できる。この
ガス導入サイクルを所望の回数繰り返せば、所望の分子
層数のGaAsが、特別な膜厚モニタを使わなくても形成で
きる。
In the case of epitaxially growing GaAs on the GaAs substrate 18 with this configuration, first, the gate valve 2 is opened, and the inside of the growth tank 1 is 10 -7 to 10 -8 Pascal (hereinafter abbreviated as Pa) by the ultrahigh vacuum exhaust device 3. ) Exhaust to the extent. Next, the GaAs substrate 18 is
After heating to 0 to 800 ° C, preferably 300 to 500 ° C by the heater 16, TMG12 is sufficiently more than the number of molecules necessary for forming one molecular layer within the range where the pressure in the growth tank 1 is 10 -1 to 10 7 Pa. Many 0.
The valve 8 is opened and introduced for 5 to 10 seconds to form a monomolecular adsorption layer. Next, after exhausting excess TMG left over from the formation of the one-molecule adsorption layer from the inside of the growth tank 1, the AsH 3 13 pressure is increased to 10%.
In the range of -1 to 10 < 7 > Pa, the number of molecules is sufficiently larger than the number of molecules required for forming one molecule adsorption layer, and the valve 5 is opened for 2 to 200 seconds for introduction. Excess AsH 3 13 left over to form the monomolecular adsorption layer is then exhausted. By the exchange surface reaction accompanying this gas introduction 1 cycle
GaAs monolayer can grow with self-stop function. By repeating this gas introduction cycle a desired number of times, GaAs having a desired number of molecular layers can be formed without using a special film thickness monitor.

続いて、このようにして成長させたGaAs分子層の上にGa
-xAlxAs1-yPyをヘテロエピタキシャル成長させる場合
は、GaAsの成長と同じようにIII族のGaとAlを導入した
後に、V族のAsとPを導入することによって1分子層が
成長でき、これを繰り返せば所望の分子層数が得られ
る。
Then, Ga is deposited on the GaAs molecular layer thus grown.
In the case of heteroepitaxial growth of -x Al x As 1-y P y , a single molecular layer is formed by introducing Group III Ga and Al and then introducing Group V As and P as in the case of GaAs growth. Growth is possible, and by repeating this, a desired number of molecular layers can be obtained.

第2図は、上記分子層エピタキシャル成長乃至ヘテロエ
ピタキシャル成長によるGa-xAlxAs1-yPy超格子半導体装
置の製造過程を示したもので、先ず、同図(a)に示す
ように、GaAs基板20上にGaAs層21を分子層単位で所定の
分子層数たとえば30分子層にエピタキシャル成長させ
る。続いて、同図(b)に示すように、そのGaAs層21上
にGa-xAlxAs1-yPy層22をやはり分子単位で所定の分子層
数たとえば40分子層を制御してヘテロエピタキシャル成
長させる。更に、以上の操作を所定の周期たとえば100
サイクル繰り返すことにより、超格子構造が形成され
る。同図(c)に示したのは3層のGaAs層21とGa1-xAlx
As1-yPy層22とを交互に分子層単位で成長させた例であ
る。このとき、GaAsに格子整合させるためのGa1-xAlxAs
1-yPyの混晶の組成はx=0.3,y=0.01とする。このよう
にして形成した超格子構造に、同図(d)に示すよう
に、Au−Ge合金を数100Å真空蒸着して電極23,24を形成
する。これは、例えば450℃、H2気流中で1分間熱処理
して形成する。これにより、超格子ダイオード25が製造
できる。第2図(c)、(d)に示したようにGaAs層21
とGa1-xAlxAs1-yPy層22との間の遷移層は全く無く、正
確に分子層単位で超格子構造が製造できる。
Figure 2 is shows the manufacturing process of Ga -x Al x As 1-y P y superlattice semiconductor device according to the molecular layer epitaxy or hetero-epitaxial growth, first, as shown in FIG. (A), GaAs A GaAs layer 21 is epitaxially grown on the substrate 20 in a predetermined number of molecular layers, for example, 30 molecular layers in a molecular layer unit. Subsequently, as shown in FIG. (B), to control the Ga -x Al x As 1-y P y layer 22 given molecular layer number also on a molecular basis, for example 40 molecule layer thereon GaAs layer 21 Heteroepitaxial growth is performed. In addition, the above operation is performed in a predetermined cycle, for example 100
By repeating the cycle, a superlattice structure is formed. FIG. 3C shows three GaAs layers 21 and Ga 1-x Al x.
This is an example in which As 1-y P y layers 22 are alternately grown in molecular layer units. At this time, Ga 1-x Al x As for lattice matching with GaAs
The composition of the mixed crystals of 1-y P y is x = 0.3, and y = 0.01. On the superlattice structure thus formed, as shown in FIG. 4D, an Au—Ge alloy is vacuum-deposited by several hundred Å to form electrodes 23 and 24. This is formed, for example, by heat treatment at 450 ° C. in a H 2 gas flow for 1 minute. Thereby, the superlattice diode 25 can be manufactured. As shown in FIGS. 2 (c) and (d), the GaAs layer 21
Since there is no transition layer between the Ga 1-x Al x As 1-y P y layer 22 and the superlattice structure can be accurately manufactured in a molecular layer unit.

ところで、上述のようにして超格子半導体を製造する
際、成長中に基板へ紫外線を照射することによって、成
長温度を300℃以下といった低温に低下させることがで
き、結晶品質を良くすることができる。この紫外線源と
しては、水銀ランプ、Xeランプ、エキシマレーザ、アル
ゴンイオンレーザ等を用いることができ、成長槽1に窓
を設け外部より基板18上に照射するようにすれば良い。
By the way, when manufacturing the superlattice semiconductor as described above, by irradiating the substrate with ultraviolet rays during the growth, the growth temperature can be lowered to a low temperature such as 300 ° C. or lower, and the crystal quality can be improved. . As the ultraviolet ray source, a mercury lamp, a Xe lamp, an excimer laser, an argon ion laser, or the like can be used, and a window may be provided in the growth tank 1 to irradiate the substrate 18 from the outside.

尚、以上の実施例においては、Ga1-xAlxAs1-yPyの超格
子半導体装置について説明してきたが、成長層糟へ更に
不純物を含むガスを導入することによって、GaAs、Ga
1-xAlxAs1-yPyへ不純物添加できることは言う迄もな
い。この場合、GaAs、Ga1-xAlxAs1-yPy共に、n形の不
純物を含むガスとして、H2SのVI族のTe,Se等の水素化
物、フッ化物を用いることができる。また、p形の不純
物としてはZnCl3、デイメチル亜鉛等のガスをIII族乃至
はV族のガスと一緒に導入すれば良い。
In the above embodiments, the superlattice semiconductor device of Ga 1-x Al x As 1-y P y has been described, but by introducing a gas containing impurities into the growth layer, GaAs, Ga
It goes without saying that impurities can be added to 1-x Al x As 1-y P y . In this case, for both GaAs and Ga 1-x Al x As 1-y P y , a hydride or fluoride of H 2 S group VI Te, Se or the like can be used as a gas containing n-type impurities. . Further, as p-type impurities, a gas such as ZnCl 3 or demethylzinc may be introduced together with a group III or group V gas.

また、超格子となる半導体の組合せは、上記の実施例を
ほかに、InAs−GaSb、GaSb−AlSb、 InAs−AlSb、InP-In1-xGaxP1-zAsz、 InP−In1-xGaxAs、GaAs−GaAs1-xPx、 GaP−GaP1-xAsx、GaAs−Ga1-xInxAs、 GaP−AlP、GaSb−InSb、Ge−GaAs、Si−GaP、 Si−Si1-xGex、CdTe−HgTe、PbTe−Pb-xSnxTe、 PbTe−Pb1-xGexTe等の組合せ、p形とn形半導体の組合
せ、3つの半導体の組合せ、例えばInAs−GaSb−AlSb等
に適用できる。
In addition, the combination of semiconductors to be a superlattice, in addition to the above examples, InAs-GaSb, GaSb-AlSb, InAs-AlSb, InP-In 1-x Ga x P 1- zAsz, InP-In 1-x. Ga x As, GaAs-GaAs 1-x P x , GaP-GaP 1-x As x , GaAs-Ga 1-x In x As, GaP-AlP, GaSb-InSb, Ge-GaAs, Si-GaP, Si- Si 1-x Ge x, CdTe -HgTe, PbTe-Pb -x Sn x Te, PbTe-Pb 1-x Ge x Te such combinations, p-type and n-type semiconductor combination, three semiconductor combinations, for example, InAs -Applicable to GaSb-AlSb, etc.

〔発明の効果〕〔The invention's effect〕

以上のように本発明によれば、半導体の結晶膜を自己停
止機能を有して分子層単位で結晶性良く低温で成長させ
ることができることから、従来のMO−CVD法等の気相成
長法で形成した超格子構造の場合に存在する異なる半導
体相互間の遷移層の全くない超格子半導体装置を工業的
に生産できるようになる。本発明によれば通常の気相成
長におけるキャリアガス、あるいはALE法におけるガス
相拡散バリアのような原料ガス以外の不活性なガスを用
いる必要もなく装置の構成が簡単となる。さらに本発明
によれば、自己停止機能による成長なのでガス導入サイ
クルを数えるのみで、膜厚モニタを必要としないため、
装置の構成や操作が容易で、分子層単位の制御ができ工
業的利点は大きい。さらに、本発明によればGaAsとGa
1-xAlxAs1-yPyとが1分子層ずつ交互に形成されるよう
な新たな超格子構造の形成も可能である。
As described above, according to the present invention, since it is possible to grow a semiconductor crystal film having a self-stop function and having good crystallinity in a molecular layer unit at low temperature, a vapor phase growth method such as a conventional MO-CVD method. The superlattice semiconductor device having no transition layer between different semiconductors existing in the case of the superlattice structure formed in 1. can be industrially produced. According to the present invention, there is no need to use an inert gas other than a raw material gas such as a carrier gas in ordinary vapor phase growth or a gas phase diffusion barrier in the ALE method, and the apparatus configuration is simplified. Furthermore, according to the present invention, since the growth is performed by the self-stop function, only gas introduction cycles are counted and a film thickness monitor is not required.
The configuration and operation of the device are easy, and the control of each molecular layer is possible, which is a great industrial advantage. Furthermore, according to the invention, GaAs and Ga
It is also possible to form a new superlattice structure in which 1-x Al x As 1-y P y and 1-x Al x As 1-y P y are alternately formed.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例に係る結晶成長装置の構成
図、第2図(a)〜(d)は第1図の装置により製造さ
れる超格子半導体装置の製造過程説明図である。 1……成長槽、2……ゲートバルブ、3……排気装置、
4〜7……ノズル、8〜11……バルブ、12〜15……ガス
源、16……ヒーター、17……熱電対、18,20……GaAs基
板、19……圧力計、21……GaAs層、22……Ga1-xAlxAs
1-yPy層、23,24……電極、25……超格子ダイオード。
FIG. 1 is a block diagram of a crystal growth apparatus according to an embodiment of the present invention, and FIGS. 2A to 2D are explanatory views of a manufacturing process of a superlattice semiconductor device manufactured by the apparatus of FIG. . 1 ... Growth tank, 2 ... Gate valve, 3 ... Exhaust device,
4-7 ... Nozzle, 8-11 ... Valve, 12-15 ... Gas source, 16 ... Heater, 17 ... Thermocouple, 18,20 ... GaAs substrate, 19 ... Pressure gauge, 21 ... GaAs layer, 22 …… Ga 1-x Al x As
1-y P y layer, 23,24 …… electrode, 25 …… superlattice diode.

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭55−130896(JP,A) 特開 昭58−98917(JP,A) Japan.J.Appl.Phy s.,19[9],(1980−9),L551〜 L554 第43回応物学会予稿集,(1982−9− 28),P.539,28P−Z−16 「応用物理」vol.53,No.6, 1984−6,P.516−520 ─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-55-130896 (JP, A) JP-A-58-98917 (JP, A) Japan. J. Appl. Phy s. , 19 [9], (1980-9), L551 to L554, 43rd Proceedings of the Society of Applied Physics, (1982-9-28), p. 539, 28P-Z-16 "Applied Physics" vol. 53, No. 6, 1984-6, P.P. 516-520

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体単結晶基板を300〜800℃に加熱し、
先端開孔部が該半導体単結晶基板表面近傍に向いた少な
く共2本のノズルを介して、III族化合物ガスとV族化
合物ガスとを成長槽内の圧力が10-1〜10-7パスカルにな
る範囲で、該成長槽の外部から前記半導体単結晶基板表
面に後退に導入し、該ノズルのそれぞれに配設されたバ
ルブの開閉と、前記成長槽内の真空排気のみにより、前
記半導体単結晶基板表面上の交換表面反応を実現し、該
交換表面反応の1サイクルに付きIII−V族化合物半導
体結晶を少なく共1分子層形成し、該サイクルを繰り返
すことにより所望の分子層数の単結晶を得る方法であっ
て、前記III族化合物ガスの導入時間が0.5〜10秒間であ
り、前記V族化合物ガスの導入時間が2〜200秒間であ
り、 (i)第1のIII−V族化合物半導体を1乃至数分子層
単位で所定の分子層数成長させる工程と、 (ii)前記第1のIII−V族化合物半導体の上に、前記
第1のIII−V族化合物半導体とは成分元素の異なる第
2のIII−V族化合物半導体を1乃至数分子層単位で所
定の分子層数成長させる工程 とを所定の回数交互に繰り返すことにより超格子半導体
構造を形成することを特徴とする超格子半導体装置の製
造方法。
1. A semiconductor single crystal substrate is heated to 300 to 800 ° C.,
The pressure of the group III compound gas and the group V compound gas in the growth tank is 10 -1 to 10 -7 pascals through at least two nozzles whose tip openings are located near the surface of the semiconductor single crystal substrate. In the range of the above, the semiconductor single crystal substrate is retreatly introduced into the surface of the semiconductor single crystal substrate from the outside of the growth tank, and the semiconductor single crystal substrate is opened and closed by opening and closing the valves and evacuating the inside of the growth tank only. An exchange surface reaction on the surface of the crystal substrate is realized, and one molecule layer of a group III-V compound semiconductor crystal is formed in a small amount in one cycle of the exchange surface reaction, and the cycle is repeated to obtain a desired number of molecular layers. A method for obtaining crystals, wherein the introduction time of the group III compound gas is 0.5 to 10 seconds, the introduction time of the group V compound gas is 2 to 200 seconds, and (i) the first III-V group The compound semiconductor is composed of a predetermined number of molecular layers in units of one to several molecular layers. And (ii) 1 to several second III-V group compound semiconductors having different constituent elements from the first III-V group compound semiconductors are provided on the first III-V group compound semiconductor. A method of manufacturing a superlattice semiconductor device, which comprises forming a superlattice semiconductor structure by alternately repeating a step of growing a predetermined number of molecular layers in a molecular layer unit a predetermined number of times.
【請求項2】特許請求の範囲第1項記載において、前記
III−V族化合物半導体結晶形成時、前記基板表面上に
は紫外光を照射して結晶品質を向上させるようにしたこ
とを特徴とする超格子半導体装置の製造方法。
2. The method according to claim 1, wherein
A method of manufacturing a superlattice semiconductor device, characterized in that the crystal quality is improved by irradiating the surface of the substrate with ultraviolet light when forming a III-V compound semiconductor crystal.
JP59153968A 1984-07-26 1984-07-26 Method for manufacturing superlattice semiconductor device Expired - Lifetime JPH0787179B2 (en)

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JPS6134922A JPS6134922A (en) 1986-02-19
JPH0787179B2 true JPH0787179B2 (en) 1995-09-20

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH078756B2 (en) * 1986-07-04 1995-02-01 日本電信電話株式会社 Compound semiconductor thin film formation method
US5270247A (en) * 1991-07-12 1993-12-14 Fujitsu Limited Atomic layer epitaxy of compound semiconductor
JPH0817161B2 (en) * 1992-11-06 1996-02-21 新技術事業団 Method for manufacturing superlattice semiconductor device
JP2567331B2 (en) * 1992-11-06 1996-12-25 新技術事業団 Method of growing compound semiconductor single crystal thin film

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FI57975C (en) * 1979-02-28 1980-11-10 Lohja Ab Oy OVER ANCHORING VIDEO UPDATE FOR AVAILABILITY
JPS5898917A (en) * 1981-12-09 1983-06-13 Seiko Epson Corp Atomic layer epitaxial device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
「応用物理」vol.53,No.6,1984−6,P.516−520
Japan.J.Appl.Phys.,19[9,(1980−9),L551〜L554
第43回応物学会予稿集,(1982−9−28),P.539,28P−Z−16

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