JPH05152304A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH05152304A
JPH05152304A JP31612091A JP31612091A JPH05152304A JP H05152304 A JPH05152304 A JP H05152304A JP 31612091 A JP31612091 A JP 31612091A JP 31612091 A JP31612091 A JP 31612091A JP H05152304 A JPH05152304 A JP H05152304A
Authority
JP
Japan
Prior art keywords
gettering
layer
semiconductor substrate
wafer
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31612091A
Other languages
Japanese (ja)
Inventor
Masanori Ohashi
正典 大橋
Hideo Kanbe
秀夫 神戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP31612091A priority Critical patent/JPH05152304A/en
Publication of JPH05152304A publication Critical patent/JPH05152304A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain a manufacturing method for a semiconductor substrate on which a gettering layer can be formed in the vicinity of a device active region in an excellent controllable manner. CONSTITUTION:First carbon is ion-implanted on the surface of a silicon wafer 11 under the condition of dosage 1X10<14> at m/cm<3>. At this point, the depth from the surface of the wafer of the high density carbon layer (gettering layer), which will be formed in the silicon wafer 11, is set at about 1mum by properly setting the energy amount of ion implantation. Then, an epitaxial layer (Si) 13 is grown in the thickness of 10 to 20mum. When an element is formed on the epitaxial layer of the semiconductor substrate formed as above, the gettering effect during processing or after formation can be maintained excellently.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体基板の製造方
法に関し、更に詳しくは、ゲッタリング層を適切な位置
に備える半導体基板の製造方法に係わる。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate having a gettering layer at an appropriate position.

【0002】[0002]

【従来の技術】ゲッタリングは、デバイス製造工程途中
において、あるいは出発材料の状態でシリコンウエハに
ある種の処理を行ない、素子形成領域にある欠陥を除去
したり有害な不純物を不活性化させる能力をもたせる技
術である。ゲッタリングの対象となる欠陥や不純物は、
積層欠陥,転移,重金属原子等であるが、ゲッタリング
技術には、大別して2つの方法がある。
2. Description of the Related Art Gettering is the ability to remove a defect in a device formation region or inactivate harmful impurities by performing a certain process on a silicon wafer during a device manufacturing process or in a state of a starting material. It is a technology that gives The defects and impurities targeted for gettering are
Although there are stacking faults, dislocations, heavy metal atoms, etc., the gettering technology is roughly classified into two methods.

【0003】その一つは、イントリンシックゲッタリン
グ(IG)であり、結晶中の酸素濃度の比較的高い(>
1〜2×1018atm/cm3)ウエハを用い、特定の
熱処理を行なうことで、酸素が結晶内で析出し、この析
出に伴なって歪が形成されてゲッタリング層となり、重
金属等を捕獲(ゲッタ)する方法である。図2は、この
イントリンシックゲッタリングを施して、シリコンウエ
ハ1の内部(表裏面の中間部)に高密度欠陥領域でなる
ゲッタリング層1Aを形成し、シリコンウエハ1表面に
エピタキシャル層2を形成した例を示している。特に、
最近CCDデバイスにおいては、白点対策として、エピ
タキシャル層を有するウエハにイントリンシックゲッタ
リングを施してデバイス歩留りを上げようとする傾向が
あり、ゲッタリングはCCDデバイスにおいては不可欠
となっている。
One of them is intrinsic gettering (IG), which has a relatively high oxygen concentration in the crystal (>).
1 to 2 × 10 18 atm / cm 3 ) A wafer is subjected to a specific heat treatment to precipitate oxygen in the crystal, and strain is formed along with the precipitation to form a gettering layer. It is a method of capturing (getter). In FIG. 2, this intrinsic gettering is applied to form a gettering layer 1A, which is a high-density defect region, inside the silicon wafer 1 (intermediate part between the front and back surfaces), and an epitaxial layer 2 is formed on the surface of the silicon wafer 1. An example is shown. In particular,
Recently, in CCD devices, as a countermeasure against white spots, there is a tendency to perform intrinsic gettering on a wafer having an epitaxial layer to increase the device yield, and gettering is indispensable in CCD devices.

【0004】他の一つの方法は、エクストリンシックゲ
ッタリング(EG)である。この方法は、ウエハ裏面に
意図的に加工キズや、CVD多結晶層などを形成してゲ
ッタリング層としたものであり、上記したイントリンシ
ックゲッタリングと同様の効果を奏する。図3は、この
エクストリンシックゲッタリングを施した例を示してお
り、シリコンウエハ1の裏面に、意図的に多結晶シリコ
ン膜3とSiO2膜4をCVD法にて形成してゲッタリ
ング層となし、シリコンウエハ1の表面にエピタキシャ
ル層2を成長させた例を示している。
Another method is extrinsic gettering (EG). This method intentionally forms a processing flaw or a CVD polycrystal layer on the back surface of the wafer to form a gettering layer, and has the same effect as the above-mentioned intrinsic gettering. FIG. 3 shows an example in which this extrinsic gettering is applied. A polycrystalline silicon film 3 and a SiO 2 film 4 are intentionally formed on the back surface of the silicon wafer 1 by a CVD method to form a gettering layer. None, an example in which the epitaxial layer 2 is grown on the surface of the silicon wafer 1 is shown.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、このよ
うな従来のゲッタリングを施した半導体基板にあって
は、以下に説明するような問題点を有している。
However, such a conventional gettering type semiconductor substrate has the following problems.

【0006】即ち、上記したイントリンシックゲッタリ
ングを施した半導体基板においては、内部に高密度欠陥
領域を作るように種々のステップを含んだ熱処理が必要
であり、例えば、高温で無欠陥層を形成し、次に温度を
下げて核形成を行ない、さらに温度を上げて長時間熱処
理を行ない、微小欠陥を酸素原子を中心として形成させ
るというように、処理工程が複雑となる。これに加え、
欠陥が少なかったり、溶存酸素濃度が少ない場合は、さ
らに複雑な熱処理工程が必要となり、これらの条件等を
デバイス毎に勘案、設定しなければならず、その制御性
に問題点がある。また、イントリンシックゲッタリング
は、相対的にゲッタ効果が低いという根本的な問題があ
る。
That is, in the above-described intrinsic gettering semiconductor substrate, it is necessary to perform heat treatment including various steps so as to form a high density defect region therein. For example, a defect-free layer is formed at a high temperature. Then, the temperature is lowered to perform the nucleation, the temperature is further raised to perform the heat treatment for a long time, and the microdefects are formed around the oxygen atoms, which complicates the treatment process. In addition to this,
When the number of defects is small or the dissolved oxygen concentration is small, a more complicated heat treatment process is required, and these conditions and the like must be taken into consideration and set for each device, and there is a problem in controllability thereof. In addition, intrinsic gettering has a fundamental problem that the gettering effect is relatively low.

【0007】一方、エクストリンシックゲッタリングを
施した半導体基板にあっては、多結晶層などのゲッタリ
ング層の剥がれや、ダストが発生し易い問題がある。ま
た、ウエハ裏面にゲッタリング層が形成されているた
め、表面側の素子形成領域から遠く離れているため、素
子形成領域付近の汚染等を充分吸収し得ない問題点があ
る。この問題点に関しては、イントリンシックゲッタリ
ングを施した半導体基板においても同様である。また、
裏面側のゲッタリング層は、ウエハがチップに加工され
た後は、パッケージングの都合上研削・除去されるた
め、そのゲッタ効果はそれ以後維持できないという問題
があった。
On the other hand, a semiconductor substrate subjected to extrinsic gettering has a problem that a gettering layer such as a polycrystalline layer is easily peeled off and dust is easily generated. Further, since the gettering layer is formed on the back surface of the wafer, the gettering layer is distant from the element forming region on the front surface side, so that there is a problem that the contamination and the like in the vicinity of the element forming region cannot be sufficiently absorbed. This problem also applies to a semiconductor substrate that has been subjected to intrinsic gettering. Also,
The gettering layer on the back surface is ground and removed after the wafer is processed into chips for the sake of packaging, so that the gettering effect cannot be maintained thereafter.

【0008】本発明は、このような従来の問題点に着目
して創案されたものであって、デバイス活性領域(素子
形成領域)付近でのゲッタ効果が高く、ゲッタリング層
形成の制御性が良い半導体基板の製造方法を得んとする
ものである。
The present invention was devised by focusing on such conventional problems, and has a high gettering effect in the vicinity of the device active region (element forming region) and controllability of the gettering layer formation. It is intended to obtain a good method for manufacturing a semiconductor substrate.

【0009】[0009]

【課題を解決するための手段】そこで、本発明は、半導
体ウエハの表面に炭素をイオン注入して該表面から浅い
位置にゲッタリング層を形成し、その後前記半導体ウエ
ハの表面に半導体エピタキシャル層を成長させること
を、その解決方法としている。
Therefore, according to the present invention, carbon is ion-implanted into the surface of a semiconductor wafer to form a gettering layer at a shallow position from the surface, and then a semiconductor epitaxial layer is formed on the surface of the semiconductor wafer. Growing up is the solution.

【0010】[0010]

【作用】半導体ウエハの表面に炭素(C)をイオン注入
することにより、制御性良くゲッタリング層を形成する
ことが可能となる。例えば、イオン注入のエネルギー,
ドーズ量を適宜設定すれば、ゲッタリング層の深さ,ゲ
ッタ作用を精度良く制御することが可能となる。このた
め、半導体ウエハの表面に形成されるエピタキシャル層
に生じた欠陥や、有害不純物は、近い位置に形成された
ゲッタリング層で吸収され易くなる。
By injecting carbon (C) into the surface of the semiconductor wafer, the gettering layer can be formed with good controllability. For example, the energy of ion implantation,
By properly setting the dose amount, the depth of the gettering layer and the gettering action can be controlled with high accuracy. Therefore, defects and harmful impurities generated in the epitaxial layer formed on the surface of the semiconductor wafer are easily absorbed by the gettering layer formed at a close position.

【0011】[0011]

【実施例】以下、本発明に係る半導体装置の製造方法の
詳細を図面に示す実施例に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method of manufacturing a semiconductor device according to the present invention will be described below with reference to the embodiments shown in the drawings.

【0012】先ず、図1(A)に示すように、ポリッシ
ュ加工が施されたシリコンウエハ11の表面より炭素
(C)を高濃度(例えば1×1014atm/cm3)で
イオン注入し、図1(B)に示すように、シリコンウエ
ハ11の表面より1μm程度の深さ位置に結晶欠陥層で
なるゲッタリング層としての高密度ガーボン層12を形
成する。
First, as shown in FIG. 1A, carbon (C) is ion-implanted at a high concentration (for example, 1 × 10 14 atm / cm 3 ) from the surface of a polished silicon wafer 11. As shown in FIG. 1B, a high-density garbon layer 12 as a gettering layer made of a crystal defect layer is formed at a depth of about 1 μm from the surface of the silicon wafer 11.

【0013】次に、シリコンウエハ11の表面に、エピ
タキシャル成長により、シリコン(Si)で成る10〜
20μm程度の厚さのエピタキシャル層13を形成す
る。
Next, 10 to 10 made of silicon (Si) is epitaxially grown on the surface of the silicon wafer 11.
The epitaxial layer 13 having a thickness of about 20 μm is formed.

【0014】このようにして形成された半導体基板は、
素子形成領域となるエピタキシャル層13と高密度カー
ボン層12とが近い距離にあり、ゲッタ効果を確実に奏
することが可能となる。特に、シリコンウエハ11の表
面に炭素をイオン注入(イオン打ち込み)することによ
り、シリコンウエハ11表面付近に高密度カーボン層1
2を制御性よく形成でき、イオン注入エネルギー,ドー
ズ量を予め設定することにより、ウエハ間に均一なゲッ
タリング層を形成することが可能となる。また、エピタ
キシャル層13に素子形成を行なった後、シリコンウエ
ハ11をチップ化してパッケージに組み立てる場合、チ
ップ下面を研削してパッケージとの密着を図ることが多
いが、ゲッタリング層である高密度カーボン層12は上
部に位置するため、除去されることなく、パッケージン
グ後もゲッタ効果を維持させることができる。
The semiconductor substrate thus formed is
Since the epitaxial layer 13 serving as the element formation region and the high-density carbon layer 12 are close to each other, the getter effect can be reliably achieved. Particularly, by ion-implanting (ion-implanting) carbon into the surface of the silicon wafer 11, the high-density carbon layer 1 is formed near the surface of the silicon wafer 11.
2 can be formed with good controllability, and by setting the ion implantation energy and the dose amount in advance, it is possible to form a uniform gettering layer between the wafers. When the silicon wafer 11 is made into chips and assembled into a package after forming elements on the epitaxial layer 13, the lower surface of the chip is often ground to achieve close contact with the package. Since the layer 12 is located on the upper side, the getter effect can be maintained even after packaging without being removed.

【0015】以上、本発明の実施例を説明したが、本発
明はこれに限定されるものではなく、構成の要旨に付随
する各種の設計変更が可能であり、例えば、イオン注入
条件その他の各種条件は設定変更が可能であることは勿
論である。
Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various design changes are possible accompanying the gist of the configuration. For example, ion implantation conditions and other various Of course, the conditions can be changed.

【0016】[0016]

【発明の効果】以上の説明から明らかなように、本発明
に係る半導体基板の製造方法は、半導体ウエハの表面に
炭素をイオン注入して該表面から浅い位置にゲッタリン
グ層を形成し、その後前記半導体ウエハの表面に半導体
エピタキシャル層を成長させることにより、ゲッタリン
グ層がデバイス活性領域付近でゲッタリングを行なうた
め、高いゲッタ効果が得られ、デバイスの信頼性を高め
る作用がある。
As is apparent from the above description, in the method for manufacturing a semiconductor substrate according to the present invention, carbon is ion-implanted into the surface of a semiconductor wafer to form a gettering layer at a shallow position from the surface, By growing the semiconductor epitaxial layer on the surface of the semiconductor wafer, the gettering layer performs gettering in the vicinity of the device active region, so that a high gettering effect is obtained and the device reliability is enhanced.

【0017】また、本発明によれば、ゲッタリング層の
形成位置,ゲッタ能力をイオン注入条件の設定で決める
ことができるため、定量的な、且つ制御性の高いゲッタ
リングが行なえる効果がある。
Further, according to the present invention, the gettering layer formation position and the gettering ability can be determined by setting the ion implantation conditions, so that there is an effect that the gettering can be performed quantitatively and with high controllability. ..

【0018】さらに、本発明によれば、従来のエクスト
リンシックゲッタリングを施した半導体基板のような膜
剥がれや、ダスト発生を回避できる効果がある。
Further, according to the present invention, there is an effect that film peeling and dust generation as in the conventional extrinsic gettering semiconductor substrate can be avoided.

【0019】また、本発明に係る方法にて製造された半
導体基板に素子形成を行ない、チップ化,パッケージ化
した後も、ゲッタ効果を維持させることが可能になり、
半導体装置の耐久性を高める効果がある。
Further, the getter effect can be maintained even after the elements are formed on the semiconductor substrate manufactured by the method according to the present invention to form chips and packages.
This has the effect of increasing the durability of the semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A),(B),(C)は本発明の実施例の各
工程を示す断面説明図。
1A, 1B, and 1C are cross-sectional explanatory views showing each step of an embodiment of the present invention.

【図2】イントリンシックゲッタリングを施した従来例
の断面説明図。
FIG. 2 is a cross-sectional explanatory view of a conventional example in which intrinsic gettering is applied.

【図3】エクストリンシックゲッタリングを施した従来
例の断面説明図。
FIG. 3 is a cross-sectional explanatory view of a conventional example to which extrinsic gettering is applied.

【符号の説明】[Explanation of symbols]

11…シリコンウエハ(半導体基板)、12…高密度カ
ーボン層(ゲッタリング層)、13…エピタキシャル
層。
11 ... Silicon wafer (semiconductor substrate), 12 ... High-density carbon layer (gettering layer), 13 ... Epitaxial layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体ウエハの表面に炭素をイオン注入
して該表面から浅い位置にゲッタリング層を形成し、そ
の後前記半導体ウエハの表面に半導体エピタキシャル層
を成長させることを特徴とする半導体基板の製造方法。
1. A semiconductor substrate comprising a semiconductor wafer, wherein carbon is ion-implanted into the surface of the semiconductor wafer to form a gettering layer at a shallow position from the surface, and then a semiconductor epitaxial layer is grown on the surface of the semiconductor wafer. Production method.
JP31612091A 1991-11-29 1991-11-29 Manufacture of semiconductor substrate Pending JPH05152304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31612091A JPH05152304A (en) 1991-11-29 1991-11-29 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31612091A JPH05152304A (en) 1991-11-29 1991-11-29 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH05152304A true JPH05152304A (en) 1993-06-18

Family

ID=18073473

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31612091A Pending JPH05152304A (en) 1991-11-29 1991-11-29 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH05152304A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734195A (en) * 1993-03-30 1998-03-31 Sony Corporation Semiconductor wafer for epitaxially grown devices having a sub-surface getter region
KR100536930B1 (en) * 1998-04-07 2005-12-14 소니 가부시끼 가이샤 Epitaxial semiconductor substrate, manufacturing method thereof, manufacturing method of semiconductor device and manufacturing method of solid-state imaging device
DE102008062040A1 (en) 2007-12-13 2009-06-18 Sumco Corporation Epitaxial wafers and process for its production
CN104823269A (en) * 2012-11-13 2015-08-05 胜高股份有限公司 Production method for semiconductor epitaxial wafer, semiconductor epitaxial wafer, and production method for solid-state imaging element
KR20160089461A (en) 2014-01-07 2016-07-27 가부시키가이샤 사무코 Epitaxial wafer manufacturing method and epitaxial wafer

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734195A (en) * 1993-03-30 1998-03-31 Sony Corporation Semiconductor wafer for epitaxially grown devices having a sub-surface getter region
US5874348A (en) * 1993-03-30 1999-02-23 Sony Corporation Semiconductor wafer and method of manufacturing same
US6140213A (en) * 1993-03-30 2000-10-31 Sony Corporation Semiconductor wafer and method of manufacturing same
KR100536930B1 (en) * 1998-04-07 2005-12-14 소니 가부시끼 가이샤 Epitaxial semiconductor substrate, manufacturing method thereof, manufacturing method of semiconductor device and manufacturing method of solid-state imaging device
DE102008062040A1 (en) 2007-12-13 2009-06-18 Sumco Corporation Epitaxial wafers and process for its production
CN104823269A (en) * 2012-11-13 2015-08-05 胜高股份有限公司 Production method for semiconductor epitaxial wafer, semiconductor epitaxial wafer, and production method for solid-state imaging element
KR20160089461A (en) 2014-01-07 2016-07-27 가부시키가이샤 사무코 Epitaxial wafer manufacturing method and epitaxial wafer
US10062569B2 (en) 2014-01-07 2018-08-28 Sumco Corporation Epitaxial wafer manufacturing method and epitaxial wafer
US10453682B2 (en) 2014-01-07 2019-10-22 Sumco Corporation Epitaxial wafer manufacturing method and epitaxial wafer
DE112014006124B4 (en) 2014-01-07 2023-06-22 Sumco Corporation Epitaxial wafer manufacturing method and epitaxial wafer
USRE49657E1 (en) 2014-01-07 2023-09-12 Sumco Corporation Epitaxial wafer manufacturing method and epitaxial wafer

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