JPH077768B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH077768B2 JPH077768B2 JP59055441A JP5544184A JPH077768B2 JP H077768 B2 JPH077768 B2 JP H077768B2 JP 59055441 A JP59055441 A JP 59055441A JP 5544184 A JP5544184 A JP 5544184A JP H077768 B2 JPH077768 B2 JP H077768B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- hours
- semiconductor substrate
- epitaxial layer
- temperature range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 9
- 230000007547 defect Effects 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、半導体装置の製造方法に関し、特にウエルを
有する半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a well.
従来例の構成とその問題点 近年、エピタキシャルウェーハは、CMOSのラッチアップ
対策として、また特性および歩留り向上を目的として、
Ｄ−RAMやCCD等に用いられている。これまで主に、エピ
タキシャルウェーハの基板がエピタキシャル層へ及ぼす
影響として考慮されていたのは、エピタキシャル成長時
における基板不純物によるオートドープや、製造プロセ
ス中の熱処理により基板不純物がエピタキシャル層へ拡
散することにより生じる実効的エピタキシャル幅の減少
等、基板不純物に関するものであった。Configuration of Conventional Example and Its Problems In recent years, epitaxial wafers have been used as a measure against CMOS latch-up and for the purpose of improving characteristics and yield.
It is used in D-RAM and CCD. Up until now, the main effects that the substrate of an epitaxial wafer has on the epitaxial layer have been considered to be auto-doping with substrate impurities during epitaxial growth and diffusion of substrate impurities into the epitaxial layer due to heat treatment during the manufacturing process. It was related to substrate impurities such as reduction of effective epitaxial width.
ところが、CMOS等のウエルを有する半導体装置において
は、ウエルを形成する工程におけるドライブインという
高温プロセス（1150℃以上、数時間〜十数時間）が原因
となって、エピタキシャル層の表面近傍に欠陥が発生す
ることがある。However, in a semiconductor device having a well such as a CMOS, a high temperature process called drive-in (1150 ° C. or higher, several hours to several tens of hours) in the step of forming the well causes defects near the surface of the epitaxial layer. May occur.
ここで、この欠陥は、半導基板に含まれている過飽和の
酸素原子が、ウエル形成時のドライブインにより、本来
は酸素濃度の低いエピタキシャル層の表面まで拡散し、
そこで析出したものである。Here, this defect is that the supersaturated oxygen atoms contained in the semiconductor substrate are diffused to the surface of the epitaxial layer, which originally has a low oxygen concentration, due to drive-in at the time of well formation.
It was deposited there.
この欠陥はリーク電流増加の原因となり、歩留りを下げ
る要因の１つとなる。This defect causes an increase in leak current and is one of the factors that lower the yield.
発明の目的 本発明は、上記欠点を解消するためになされたもので、
半導体装置、特にエピタキシャルウェーハを用いたウエ
ルを有する半導体装置において、リーク電流を低減させ
る半導体装置の製造方法を提供するものである。OBJECT OF THE INVENTION The present invention has been made to solve the above drawbacks,
Provided is a method for manufacturing a semiconductor device, particularly a semiconductor device having a well using an epitaxial wafer, which reduces a leak current.
発明の構成 本発明は、CZ法による半導体基板上にエピタキシャル層
を成長させた後、前記半導体基板を600℃〜800℃の低温
域の温度で数十時間、好ましくは30時間程度熱処理を行
う第１工程と、前記第１工程後に、前記低温域の温度以
上1000℃以下の中温域の温度で数時間、好ましくは６時
間程度熱処理を行う第２工程と、前記第２工程後に、11
50℃以上の高温域で数時間熱処理を行い、ウエルを形成
する第３工程とを含むことを特徴とする半導体装置の製
造方法であり、これにより、表面欠陥の発生を防止する
作用を得るものである。Structure of the invention The present invention is, after growing an epitaxial layer on the semiconductor substrate by the CZ method, the semiconductor substrate is subjected to a heat treatment for several tens of hours at a low temperature range of 600 ° C ~ 800 ° C, preferably about 30 hours. 1 step, a second step after the first step, and a heat treatment for a few hours, preferably about 6 hours at a temperature in the intermediate temperature range of not less than 1000 ° C. and not more than 1000 ° C., and after the second step, 11
A method of manufacturing a semiconductor device, comprising a third step of forming a well by performing heat treatment in a high temperature range of 50 ° C. or higher for obtaining a function of preventing generation of surface defects. Is.
実施例の説明 以下本発明の一実施例について、図面を参照しながら説
明する。Description of Embodiments An embodiment of the present invention will be described below with reference to the drawings.
図は本発明により形成された半導体装置の構造断面図で
ある。The figure is a structural cross-sectional view of a semiconductor device formed according to the present invention.
半導体基板１上に、前記半導体基板と同一導電型のエピ
タキシャル層２を10〜20μｍ成長させる。そして700℃,
30時間の熱処理と、1000℃,6時間の熱処理を施すことに
より、欠陥３を形成させる。その後選択的に半導体基板
１の導電型と反対の導電型のイオンを注入し、1200℃,6
時間のドライブインを行ないウエル４を形成する。An epitaxial layer 2 of the same conductivity type as the semiconductor substrate is grown on the semiconductor substrate 1 by 10 to 20 μm. And 700 ℃,
Defects 3 are formed by performing heat treatment for 30 hours and heat treatment at 1000 ° C. for 6 hours. After that, ions of a conductivity type opposite to the conductivity type of the semiconductor substrate 1 are selectively implanted, and the temperature is set to 1200 ° C., 6
Well 4 is formed by time-in drive-in.
このように、低温と中温の熱処理を施せば、半導体基板
１内にのみ酸素を析出させた欠陥３が形成される。これ
により、基板１の酸素濃度は低下し、ドライブインによ
る酸素の表面拡散を減少させることができる。その結
果、エピタキシャル層２の酸素濃度は、欠陥発生臨界値
以上にはならず、エピタキシャル層２は、抵抗率変化の
少ない、無欠陥領域として保持される。また、従来は無
欠陥領域の幅を、薄く精度良く形成することは困難であ
ったが、本発明の方法によると、かなり精度よく形成す
ることができる。これにより、疑似信号対策およびゲッ
タリング効果がより有効に行なえるようになる。As described above, when the low-temperature and medium-temperature heat treatments are performed, the defects 3 in which oxygen is precipitated are formed only in the semiconductor substrate 1. As a result, the oxygen concentration of the substrate 1 is lowered, and the surface diffusion of oxygen due to the drive-in can be reduced. As a result, the oxygen concentration of the epitaxial layer 2 does not exceed the defect generation critical value, and the epitaxial layer 2 is held as a defect-free region with a small change in resistivity. Further, conventionally, it was difficult to form the width of the defect-free region thinly and with high precision, but according to the method of the present invention, it can be formed with considerably high precision. As a result, the pseudo signal countermeasure and the gettering effect can be more effectively performed.
発明の効果 以上述べたように、本発明による半導体装置の製造方法
は、ウェルを有する半導体装置に適用すれば、表面欠陥
の発生を防止することにより、リーク電流を減少させる
ことができ、その実用的効果は大なるものがある。As described above, the method for manufacturing a semiconductor device according to the present invention, when applied to a semiconductor device having a well, can prevent the generation of surface defects and thereby reduce the leak current. There is a great effect.
図は、本発明により形成された半導体装置の断面図であ
る。 １……半導体基板、２……エピタキシャル層、３……酸
素析出による欠陥、４……ウェル。The figure is a cross-sectional view of a semiconductor device formed according to the present invention. 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 3 ... Defects due to oxygen precipitation, 4 ... Well.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 広島 義光 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (56)参考文献 特開 昭58−138034（ＪＰ，Ａ) 特開 昭57−17125（ＪＰ，Ａ) 特開 昭58−56462（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshimitsu Hiroshima, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-58-138034 (JP, A) JP-A-57-17125 (JP, A) JP 58-56462 (JP, A)
Claims (1)
層を成長させた後、前記半導体基板を600℃〜800℃の低
温域の温度で数十時間、好ましくは30時間程度熱処理を
行う第１工程と、前記第１工程後に、前記低温域の温度
以上1000℃以下の中温域の温度で数時間、好ましくは６
時間程度熱処理を行う第２工程と、前記第２工程後に、
1150℃以上の高温域で数時間熱処理を行い、ウエルを形
成する第３工程とを含むことを特徴とする半導体装置の
製造方法。1. A first step in which an epitaxial layer is grown on a semiconductor substrate by the CZ method, and then the semiconductor substrate is heat-treated at a low temperature range of 600 ° C. to 800 ° C. for several tens of hours, preferably about 30 hours. And, after the first step, at a temperature in the intermediate temperature range of not lower than the low temperature range and not higher than 1000 ° C. for several hours, preferably 6
A second step of performing heat treatment for about an hour, and after the second step,
And a third step of forming a well by performing heat treatment in a high temperature range of 1150 ° C. or higher for several hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055441A JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055441A JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60198735A JPS60198735A (en) | 1985-10-08 |
| JPH077768B2 true JPH077768B2 (en) | 1995-01-30 |
Family
ID=12998679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59055441A Expired - Lifetime JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077768B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01312840A (en) * | 1988-06-10 | 1989-12-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH022624A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| KR100760736B1 (en) * | 2000-01-26 | 2007-09-21 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing process for silicon epitaxial wafer |
| JP2010161237A (en) * | 2009-01-08 | 2010-07-22 | Toyota Motor Corp | Method of manufacturing semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5717125A (en) * | 1980-07-04 | 1982-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5856462A (en) * | 1981-09-30 | 1983-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58138034A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-03-22 JP JP59055441A patent/JPH077768B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60198735A (en) | 1985-10-08 |
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