JPS60198735A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60198735A JPS60198735A JP59055441A JP5544184A JPS60198735A JP S60198735 A JPS60198735 A JP S60198735A JP 59055441 A JP59055441 A JP 59055441A JP 5544184 A JP5544184 A JP 5544184A JP S60198735 A JPS60198735 A JP S60198735A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor substrate
- epitaxial layer
- semiconductor device
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本品明け、半導体装置の製造方法に関し、特にウェルを
有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a well.
従来例の構成とその問題点
近年、エピタキシャルウェーハは、０ＭＯ３のラノチア
ッグ対策として、また特性および歩留逆向上を目的とし
て、Ｄ−ＲＡＭやＣＯＤ等に用いられている。これまで
主に、エピタキシャルウェーハの基板がエピタキシャル
層へ及ぼす影響として考慮されていたのは、エピタキシ
ャル成長時における基板不純物によるオートドープや、
製造プロセス中の熱処理により基板不純物がエピタキシ
ャル層へ拡散することによシ生じる実効的エピタキシャ
ル層の減少等、基板不純物に関するものであった。Conventional Structures and Problems In recent years, epitaxial wafers have been used for D-RAMs, CODs, etc. as a countermeasure against 0MO3 lanotiag and for the purpose of reversely improving characteristics and yield. Until now, the effects that the epitaxial wafer substrate has on the epitaxial layer have mainly been considered, such as autodoping caused by substrate impurities during epitaxial growth,
The issues concerned substrate impurities, such as a reduction in the effective epitaxial layer caused by diffusion of substrate impurities into the epitaxial layer due to heat treatment during the manufacturing process.
ところが、０ＭＯ８等のウェルを有する半導体装置にお
いては、ウェルを形成する工程におけるドライブインと
いう高温プロセス（１１６０℃以上、数時間〜十数時間
）が原因となって、エピタキシャル層の表明近傍に欠陥
が発生することがある。However, in semiconductor devices having wells such as 0MO8, defects occur near the surface of the epitaxial layer due to the high-temperature drive-in process (1160°C or higher, several hours to more than 10 hours) in the process of forming the well. This may occur.
ここで、この欠陥は、半導基板に含まれている過飽和の
酸素原子が、ウェル形成時のドライブインにより、本来
は酸素濃度の低いエピタキシャル層の表面まで拡散し、
そこで析出したものである。Here, this defect occurs because supersaturated oxygen atoms contained in the semiconductor substrate diffuse to the surface of the epitaxial layer, which originally has a low oxygen concentration, due to drive-in during well formation.
This is what was precipitated there.
この欠陥はリーク電流増り口の原因となシ、歩留りを下
げる要因の１つとなる。This defect causes an increase in leakage current and is one of the factors that lowers the yield.
発明の目的
本発明は、上記欠点を解消するためになされたもので、
半導体装置、特にエビタキシャルウエーハを用いたウェ
ルを有する半導体装置において、リーク電流を低減させ
る半導体装置の製造方法を提供するものである。Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks.
The present invention provides a method for manufacturing a semiconductor device that reduces leakage current in a semiconductor device, particularly in a semiconductor device having a well using an epitaxial wafer.
発明の構成
本発明は、基板上にエピタキシャル層を成長させた後、
６００〜８００ＩＣで数十時間、１０００’Ｃ程度で数
時間程度の熱処理を行う工程を含む半導体装置の製造方
法である。Structure of the Invention The present invention provides the following methods: After growing an epitaxial layer on a substrate,
This method of manufacturing a semiconductor device includes a step of performing heat treatment at 600 to 800 IC for several tens of hours and at about 1000'C for several hours.
実施例の説明
以下本発明の一実施例に？いて、図面を参照しながら説
明する。DESCRIPTION OF EMBODIMENTS The following is an embodiment of the present invention. This will be explained with reference to the drawings.
図は本発明によシ形成された半導体装置の構造断面図で
ある。The figure is a structural sectional view of a semiconductor device formed according to the present invention.
半導体基板１上に、前記半導体基板と同一導電型のエピ
タキシャル層２を１０〜２０μｍ 成長すせる。そして
７００”Ｃ，３０時間の熱処理と、１０００”Ｃ，６時
間の熱処理を施すことによシ、欠陥３を形成させる。そ
の後選択的に半導体基板１の導電型と反対の導電型のイ
オンを注入し、１２００’Ｃ，６時間のドライブインを
行ないウェル４を形成する。On a semiconductor substrate 1, an epitaxial layer 2 having the same conductivity type as the semiconductor substrate is grown to a thickness of 10 to 20 μm. Defects 3 are formed by heat treatment at 700''C for 30 hours and heat treatment at 1000''C for 6 hours. Thereafter, ions of a conductivity type opposite to that of the semiconductor substrate 1 are selectively implanted, and drive-in is performed at 1200'C for 6 hours to form a well 4.
このように、低温と中温の熱処理を施せば、半導体基板
１内′にのみ酸素を析出させた欠陥３が形成される。こ
れによシ、基板１の酸素濃度は低下し、ドライブインに
よる酸素の表面拡散を減少させることができる。その結
果、エピタキシャル層２の酸素濃度は、欠陥発生臨界値
以上にはならず、エピタキシャル層２は、抵抗率変化の
少ない、無欠陥領域として保持される。また、従来は無
欠陥領域の幅を、薄く精度良く形成することは困難であ
ったが、本発明の方法によると、かなり精度よく形成す
ることができる。これによシ、擬似信号対策およびゲッ
タリング効果がよシ有効に行なえるようになる。As described above, by performing heat treatment at low and medium temperatures, defects 3 in which oxygen is precipitated only within the semiconductor substrate 1' are formed. As a result, the oxygen concentration in the substrate 1 is reduced, and surface diffusion of oxygen due to drive-in can be reduced. As a result, the oxygen concentration in the epitaxial layer 2 does not exceed the defect generation critical value, and the epitaxial layer 2 is maintained as a defect-free region with little change in resistivity. Further, although it has conventionally been difficult to form the width of the defect-free region thinly and accurately, according to the method of the present invention, it can be formed with considerable precision. This makes it possible to more effectively take measures against false signals and gettering effects.
発明の効果
以上述べたように、本発明による半導体装置の製造方法
は、ウェルを有する半導体装置に適用すれば、表面欠陥
の発生を防止することによシ、リーク電流を減少させる
ことができ、その実用的効果は大なるものがある。Effects of the Invention As described above, when the method for manufacturing a semiconductor device according to the present invention is applied to a semiconductor device having a well, leakage current can be reduced by preventing surface defects from occurring. Its practical effects are significant.
図は、本発明によシ形成された半導体装置の断面図であ
る。
１・・・・・・半導体基板、２・・・・・・エピタキシ
ャル層、３・・・・・・酸素析出による欠陥、４・・・
・・・ウェル。The figure is a cross-sectional view of a semiconductor device formed according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Epitaxial layer, 3... Defects due to oxygen precipitation, 4...
...well.
Claims (1)
せた後、前記半導体基板を数十時間程度の６００〜Ｂ
ｏ ｏ ’ｃ熱処理を行う工程と、数時間程度の１００
０’Ｃ程度の処理を行う工程とを含むことを特徴とする
半導体装置の製造方法。After growing an epitaxial layer on a semiconductor substrate by the CZ method, the semiconductor substrate is heated at 600~B for about several tens of hours.
o o 'c heat treatment process and 100% heat treatment for several hours
A method for manufacturing a semiconductor device, comprising the step of performing treatment at approximately 0'C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055441A JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055441A JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60198735A true JPS60198735A (en) | 1985-10-08 |
| JPH077768B2 JPH077768B2 (en) | 1995-01-30 |
Family
ID=12998679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59055441A Expired - Lifetime JPH077768B2 (en) | 1984-03-22 | 1984-03-22 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH077768B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01312840A (en) * | 1988-06-10 | 1989-12-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH022624A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| WO2001056071A1 (en) * | 2000-01-26 | 2001-08-02 | Shin-Etsu Handotai Co., Ltd. | Method for producing silicon epitaxial wafer |
| JP2010161237A (en) * | 2009-01-08 | 2010-07-22 | Toyota Motor Corp | Method of manufacturing semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5717125A (en) * | 1980-07-04 | 1982-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5856462A (en) * | 1981-09-30 | 1983-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58138034A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-03-22 JP JP59055441A patent/JPH077768B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5717125A (en) * | 1980-07-04 | 1982-01-28 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS5856462A (en) * | 1981-09-30 | 1983-04-04 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS58138034A (en) * | 1982-02-12 | 1983-08-16 | Nec Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01312840A (en) * | 1988-06-10 | 1989-12-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH022624A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| WO2001056071A1 (en) * | 2000-01-26 | 2001-08-02 | Shin-Etsu Handotai Co., Ltd. | Method for producing silicon epitaxial wafer |
| KR100760736B1 (en) * | 2000-01-26 | 2007-09-21 | 신에쯔 한도타이 가부시키가이샤 | Manufacturing process for silicon epitaxial wafer |
| JP2010161237A (en) * | 2009-01-08 | 2010-07-22 | Toyota Motor Corp | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH077768B2 (en) | 1995-01-30 |
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