JPS5887833A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form unclei of crystal defect inside of the bulk according to the heat treatment of a comparatively short time at the low temperature treatment to make the crystal defect nuclei to grow by a method wherein the temperature of a semiconductor substrate is made to rise from the starting temperature of 450-950 deg.C up to a high temperature. CONSTITUTION:A single crystal silicon wafer 1 manufactured according to the Czochralski method is treated in dry nitrogen gas for one hour at about 1,200 deg.C, a solid solution of oxygen at the neighborhood of the surface to form an element is made to diffuse outward, and a no defect region (denuded zone) 2 of about 10mum thickness is formed in the surface of the wafer. After the wafer 1 thereof is treated for 3hr in dry nitrogen gas at 650 deg.C, the temperature is made to rise by 1 deg.C/min up to 900 deg.C, and the nuclei 3 of crystal defect are formed only inside of the bulk. After then, a polycrystalline silicon layer is formed on the whole surface of the silicon wafer according to the deposition technique, and it is formed into a gate electrode 7 and the other wirings according to the etching technique.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing various semiconductor devices including integrated circuits such as ICs and LSIs, and particularly relates to a method of processing a single crystal semiconductor substrate constituting a semiconductor device.

Among the things that degrade the characteristics of semiconductor devices are defects and harmful impurities that are induced within the semiconductor substrate during the manufacturing process. In order to remove these, various gettering methods have been proposed for the single crystal semiconductor base material.

Typical examples include methods of mechanically damaging the backside of a semiconductor wafer (substrate), methods of high-concentration ion implantation or high-concentration impurity diffusion into the backside of the wafer, and JJC, e.
There is an oxidation method, and more recently there is a) intrinsic method that does not intentionally create crystal defects only inside the silicon wafer.
Maybe gettering method.

However, for these semiconductor substrates, conventional gettering methods (44), except for intrinsic fist gettering,
There are problems in the production of contamination, etc. and constraints on the heat treatment conditions for ψ.Also, in the IJ method, the heat treatment time is long,
Particularly problematic is the long low-temperature treatment that forms crystal defect nuclei within the bulk.

Therefore, it is an object of the present invention to provide a heat treatment method for a semiconductor substrate that eliminates the disadvantages of the conventional intrinsic getter 1-Nong method mentioned above and forms crystal defect nuclei within the bulk with a relatively short heat treatment. In addition, we aim to develop semiconductor devices with good characteristics using these semiconductor substrates.
The objective is to provide a manufacturing method for obtaining.

In order to achieve this objective, according to the present invention, in a low temperature heat treatment for growing crystal defect nuclei,
For semiconductor substrates from a starting temperature of 50C to high temperatures? li [
It is characterized by increasing -1-.

In general, silicon single crystals grown by the Czochralski method are processed (-7) In semiconductor substrates, the nucleation of crystal defects inside the bulk takes advantage of the precipitation phenomenon of solid solute oxygen atoms θ contained in supersaturation. 1. In order to increase the bulk defect density, the process is carried out at a low temperature with a high degree of supersaturation. However, in this low-temperature treatment, in order to form defect nuclei with a sufficient diameter, it is necessary to maintain the temperature at a constant temperature for a long time, for example, 16 hours or more. Furthermore, defect nuclei grow to a sufficiently stable size even when the wafer surface area is made defect-free by outward diffusion of oxygen atoms during subsequent high-temperature treatments, including heat treatment during the semiconductor device manufacturing process. In order to achieve this, long-term heat treatment (for example, 16 hours or more) is required. On the other hand, the present invention focuses on the fact that the growth of defect nuclei becomes faster when the temperature is raised, and increases the temperature of the semiconductor substrate at a rate that does not eliminate the defect nuclei formed at low temperatures, thereby allowing the nuclei to grow. It is characterized by promoting This σ
) By performing the temperature raising treatment, it is possible to significantly shorten the heat treatment time for the growth of defect nuclei, and moreover, it is possible to exhibit a sufficient gettering effect.

In the treatment method of the present invention, the rate of temperature increase from a starting temperature of 450 to 950 C is preferably 5 C/mm or less, more preferably 1 to 3 C/mm.

This temperature increase rate can satisfy both the objectives of the present invention, which are shortening of processing time and growth of defect nuclei of sufficient size. In other words, increasing the temperature improves the oxygen diffusion rate in the bulk, but if the temperature increasing rate is too high, the actual nuclear radius will be smaller than the critical radius determined by the temperature, and the defective nuclei will It becomes unstable and easily melts and disappears. This phenomenon has a strong tendency to occur when the temperature increase rate exceeds 5 C/mm, so the upper limit is preferably 5 C/ml, and the preferable rate range is 1 to 3 C/mlfi.

Further, this heat treatment should start at a relatively low temperature of 450 to 950C. This is because at temperatures below 450C, the temperature is too low and the oxygen diffusion rate becomes extremely low, and at temperatures above 950C, the supersaturation of 02 is insufficient and its nucleus growth cannot be expected; This is because it disappears.

Therefore, as in the method of the present invention, if the starting temperature is set at 450 to 950C and the temperature of the substrate is increased (temperature change) in order to sufficiently grow defect nuclei, the temperature can be increased within a short time (within 10 hours). For example, a sufficient nucleus size for gettering action can be obtained in 5-6 hours) and then 10
A layer of minute defects such as Sin, precipitates, dislocations, stacking faults, etc. is generated during specially provided high-temperature treatment of 00 C or more or during high-temperature treatment during the device manufacturing process, and this minute defect layer serves as a getter for unnecessary impurities. 1) A defect-free layer can be formed in the vicinity of the surface of the semiconductor substrate.

Hereinafter, embodiments of the present invention shown in the drawings will be described in more detail.

FIGS. 1(a) to (h) show MO8IC to which the present invention is applied.
FIG. 2 is a cross-sectional view showing a manufacturing method.

First, as shown in FIG. 1(a), a single crystal silicon wafer 1 manufactured by the Czochralski method is
The wafer is treated with 200C for 11 hours in dry nitrogen to diffuse out the solid solution oxygen in the vicinity of the surface forming the device, thereby forming a defect-free region (denuded zone) 2 of about 10 μm on the wafer surface.

Next, as shown in FIG. 1(b), this wafer 1 was treated at 6501Z in dry nitrogen for 3 hours, and then heated to 900C at a rate of 1'Q,/mm to eliminate crystal defects only inside the bulk. 3 to form a nucleus 3, then l 1 f'I O as shown in Figure 1 fc)
Thermal oxidation for 4 hours in the high temperature of C steam,
A silicon oxide film 4 of about 700 OA is formed. After this θ), as shown in FIG. 1(d), the silicon eKtJ4 in the area where the MOS FIl (insulated gate type ``superior field effect transistor'') is to be formed is removed by etching technology. Hole fNli 5 in silicon oxide film 4
Form 'a'.

Subsequently, the silicon wafer 1 is thermally oxidized for 50 minutes in a dry oxygen atmosphere of 100 OC to form a gate silicon oxide film 6 having a thickness of about 50 OA.

Furthermore, as shown in Fig. 1(fe), a polycrystalline silicon layer is formed on the entire surface of the silicon wafer using a deposition technique (t7), and then the gate is patterned according to the shape of the pole and other interconnections using an etching technique. The electrodes 7 and other interconnections (not shown) are formed on the gate +-'.

Next, as shown in FIG. 1(if), the surfaces of the silicon oxide films 6 and 4 are removed by an etching technique to the extent that the thin silicon oxide film 6 exposed from the gate electrode 7 is removed. This exposes the silicon wafer surface where the source and drain are to be formed.

Further, as shown in FIG. 1(e), phosphorus, which is an N-type impurity, is deposited at a temperature of about 10,001:1' through the exposed portion, and is diffused into the source and drain regions 8. Form .9.

Next, as shown in FIG. 1(h), a phosphorus siligate glass (PSG) film 10 is formed on the entire surface, and a hole for a contact in this phosphorus siligate glass film 10 is formed by a subsequent etching process. 12. Using ordinary aluminum vapor deposition technology and aluminum etching technology,
Aluminum electrodes 11 and 12, j and other aluminum interconnections (not shown) are formed in ohmic contact with the source and drain regions, respectively.
' is formed.

According to the above manufacturing process, one defect nucleus 3 is grown in a short-time low temperature treatment (Fig. 1b) while the surface area for forming the element is made defect-free (Fig. 1a), and then Further, heat treatments such as thermal oxidation and diffusion in the IC manufacturing process itself form crystal defects 3 and 12, thereby providing a gettering effect to make the element formation region near the surface of the wafer a defect-free layer. Therefore, crystal defects and harmful impurities in the element region are removed, and characteristics such as reverse breakdown voltage, leakage, and noise, and yield are improved.

FIG. 2 shows the experimental results and is a diagram showing the relationship between low temperature treatment conditions and bulk crystal defect density.

This figure is shown in Figure 3 (as shown in bj for high temperature treatment)
After heat treatment in 200 tr, dry nitrogen, low temperature treatment was kept in 650C1 dry nitrogen for 1-3 hours, then 900C
The temperature was increased at a rate of 1'c or 3C/m until
It shows the bulk defect density when heat treated in 000C1 dry oxygen for 16 hours, where curve A is IC/IMn and curve B is 3U 7mm (n).When the heating rate is IC/mvr Sometimes, a high density of bulk defects occurs regardless of the holding time at 650C, but when the heating rate is 3C/
In the case of min, the bulk defect density also increases as the holding time at 650C increases. The high-density σ) bulk defects formed in this way have a density similar to that of bulk defects when nucleation is performed by low-temperature treatment at a constant temperature of 650 C for 16 hours (heat treatment sequence Figure 3 (a)). . Therefore, using the method of the present invention, in) IJ
The formation of bulk crystal defects required for non-thick gettering can be achieved with a shorter heat treatment time than conventional methods.

The present invention aims to provide a method of low temperature processing in intrinsic gettering, and an example of a temperature sequence until the completion of a semiconductor device by applying the present invention will be described with reference to FIG. 3(b).

During time T1 in FIG. 3(b), the prepared silicon wafer is heat treated at a high temperature of 1200 t:' for 1 hour to cause out-diffusion of interstitial oxygen near the surface of the wafer.

If this treatment is performed, no minute defects will be generated near the surface.

Then, at t... of time 'r, initially 65
Heat treatment was carried out at a temperature of 0C for 1 hour, followed by 650C.
Gradually raise the temperature from C to 900 C. This place mackerel 'I'
Precipitation nuclei are formed in the cold-treated intercostals of 2. Thereafter, in the period 'I'3, thermal oxidation, diffusion, etc. are performed to form the element. In the second stage, high temperature of 1000iC to 1250C is applied intermittently or continuously to grow the nucleus.・Europe, where micro defects are generated by
The surface layer near the surface of the wafer becomes defect-free, and as a result, semiconductor devices are completed within the defect-free layer within the wafer. Note that during the heat treatment period rr, the wafer may be specially heat-treated before forming devices, and the heating time may be continuous or intermittent. Note that the time 1'' in FIG. 3(b) is schematically shown as the total heating time (for example, 16 hours) during the manufacturing process.

According to the temperature sequence according to the present invention as shown in FIG. 3(b), the low temperature treatment is carried out at a constant temperature for a long period of time as shown in FIG. 3(a). (for example, 16 hours), the processing time can be significantly reduced. A wafer manufactured under the same manufacturing conditions as the wafer in FIG. 3(b) is shown in FIG. 3(a).
When performing low-temperature treatment with the temperature sequence shown in Figure 3(b)
In order to obtain a gettering effect equivalent to the above, heat treatment at a constant temperature of 650C for 16 hours or more is required. This is the third
In contrast to the low-temperature treatment shown in Figure (b), which requires less than 10 hours, there is a drawback in that it requires an extremely long treatment time.

As is clear from the temperature sequences shown in FIGS. 3(a) and 3(b), the method of the present invention shown in FIG. Can be shortened. In that case, the moisture resistance speed is typically 1~
The starting temperature (650C) is maintained for a certain period of time before increasing the temperature, and the defect nuclei are allowed to grow to a sufficiently stable size within this holding time. The nuclear radius (size) is increased when the temperature is increased (
(See Figure 2). Further, the final temperature of this temperature increase may be about 900C as shown in Fig.
0~1250t? manufacturing process temperature (e.g. 100O
The temperature may be raised continuously to U). In the figure, in period 11NI, the cutting tool was subjected to high-temperature heat treatment for outward diffusion of oxygen at 1000-1300C for 1-4 hours.
The low-temperature heat treatment time for defect nucleus growth in period T is within 10 hours (5 to 6 hours in military form), and in the period 'r after low-temperature treatment, the formation of a defect-free layer on the surface and the formation of a defect-free layer on the surface. The high temperature treatment for formation may be at a temperature of 1000-1250C for 10-20 hours (eg 16 hours). When using a semiconductor device (element) manufacturing process, high-temperature treatment after low-temperature treatment is defined by the treatment time and temperature of the same process, but as mentioned above, it is a heat treatment process added separately from the manufacturing process. You can also use it as

Incidentally, in each temperature sequence, the start of each process and the rise and fall of the final temperature are actually performed gradually over a certain time range, but are simplified in the drawings.

The low-temperature treatment of the substrate for nucleation in the present invention can be performed by increasing the temperature or by other variations on the temperature profile described above. As shown in FIG. 5, for example, for the profile A described above, if the temperature is raised immediately from the start as shown by the broken line Bσ), the time can be further shortened, and the time can be further shortened by the dashed line C
If the temperature is raised in a quadratic curve like this, sufficient nucleus growth will occur at the initial stage, and a sufficient size of the nuclei can be obtained even when the temperature is raised at a steep slope thereafter. Moreover, if the structure is set as shown by the two-dot chain line, defect growth is also realized from the nucleus growth, so that the process from the nucleus growth to the defect growth can be carried out continuously. The starting temperature of this low-temperature treatment is 65 (not limited to IC), 600 to 8
0 (IU) is practical and allowable in the range of 450 to 950C.In short, JJ1 temperature for nuclear growth may be performed in the range of 450 to 950C.

Unlike FIG. 3(b), FIG. 4 shows an example in which high-temperature heat treatment for outward diffusion of oxygen 02 is performed after low-temperature treatment. In this case as well, gettering effects due to defect growth can be expected. However, the nuclei grown in the first low-temperature treatment (still minute in size at this point) will easily dissolve during the next high-temperature treatment, so it is necessary to ensure that the first low-temperature treatment is sufficient to increase the size of the nuclei. Therefore, the processing time becomes longer than in FIG. 3(b). It is also possible to omit the above-mentioned high-temperature treatment in the process shown in FIG. Diffusion and internal defect growth are performed at the same time, which simplifies the process itself.

(19) The present invention is not limited to the embodiments described above, and may be incorporated into the device manufacturing process. This can also be achieved by moving the semiconductor substrate in a furnace.

[Brief explanation of drawings]

FIGS. 1(a) to 1(h) are cross-sectional views showing the manufacturing method of MO8IC, which is an embodiment of the present invention, in order of process, and FIG. 2 shows the relationship between low-temperature heat treatment conditions and bulk crystal defect density. 3(a), 3(b), and 4 are graphs showing the temperature profile depending on the processing time, and FIG. 5 is a graph showing the temperature increase during the low temperature processing. 1... Silicon wafer, 2... Defect-free region (denuded zone), 3... Defect nucleus or bulk crystal defect, 4... Thermal oxide film, 5... Hole, 6-... For gate Insulating film, 7... Gate electrode, 8... Source region, 9...
...Drain region, 10.. Rinph 11 Kate glass film, 11.. Source electrode, 12. Drain region. ! ! Jurisdiction? 1% arrow and

Claims (1)

[Scope of Claims] A step of heat-treating the semiconductor substrate while raising the temperature from a starting temperature in the range of 1.450 to 950 C, and during this step, at least before, crystal defect nuclei are formed inside the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising growing a semiconductor device. 2. The method according to claim 1, wherein the temperature increase rate of the semiconductor substrate is 5 C/mi or less. 3. The method described in claim 1 or 2, wherein the semiconductor substrate is held at a starting temperature for a certain period of time and then continuously raised to a high temperature. 4. The method according to claim 1 or 2, in which the temperature of the semiconductor substrate is raised continuously from the start of the process to the end of the process. 5. A method according to any one of claims 1 to 4, which grows crystal defect nuclei inside a semiconductor substrate and further promotes this growth to produce crystal defects that have a gettering effect. The method described. 6. The method according to claim 5, which comprises a heat treatment step of raising the temperature of the semiconductor substrate to a high temperature of 950C or lower and then maintaining the temperature at 1OOOC or higher to sufficiently generate crystal defects. 7. The temperature of the semiconductor substrate is continuously raised from a starting temperature of 450 to 950 C to a high temperature of 1000 C or more that sufficiently generates crystal defects, and maintained at this high temperature. A method according to claim 5. 8. The method described in any one of claims 1 to 7, wherein the semiconductor substrate is previously subjected to heat treatment at 1000C or higher.