JPS63227026A - Gettering method for silicon crystal substrate - Google Patents

Gettering method for silicon crystal substrate

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Publication number
JPS63227026A
JPS63227026A JP6181787A JP6181787A JPS63227026A JP S63227026 A JPS63227026 A JP S63227026A JP 6181787 A JP6181787 A JP 6181787A JP 6181787 A JP6181787 A JP 6181787A JP S63227026 A JPS63227026 A JP S63227026A
Authority
JP
Japan
Prior art keywords
silicon crystal
heat treatment
crystal substrate
gettering
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6181787A
Other languages
Japanese (ja)
Inventor
Hiroshi Kaneda
寛 金田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6181787A priority Critical patent/JPS63227026A/en
Publication of JPS63227026A publication Critical patent/JPS63227026A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the gettering efficiency of a silicon crystal substrate by intrinsically gettering a semiconductor device of the structure in which an epitaxial layer of film thickness replaced as a nondefect layer is formed on the substrate containing high carbon concentration. CONSTITUTION:After a crystal substrate 5 formed in thickness of approx. 5-50mum on which a silicon epitaxial layer 7 is formed by an epitaxial growing method on the surface of a high carbon concentration lifting silicon crystal 6 containing approx. 0.5-15ppma of carbon is first heat-treated to form a microdefect region in the crystal 6, and it is second heat-treated at higher temperature than that at the time of first heat treatment Since a heat treatment for forming the nondefect layer on the substrate surface is eliminated, total heat-treating time can be shortened to efficiently intrinsically getter it.

Description

【発明の詳細な説明】 〔概要〕 本発明は、表面にエピタキシャル層が形成されているシ
リコン結晶基板内部に微小欠陥を作り、シリコン結晶基
板自体にゲッタリング能力をもたせるイントリンシック
ゲッタリング(IG)方法において、 高炭素濃度としたシリコン結晶基板上に、無欠陥層とし
て代用する膜厚のエピタキシャル層が形成された構造の
半導体装置に対してイントリンシックゲッタリングを行
なうことにより、ゲッタリング効率を従来の方法に比べ
て向上するようにしたものである。
[Detailed Description of the Invention] [Summary] The present invention provides intrinsic gettering (IG) in which micro defects are created inside a silicon crystal substrate on which an epitaxial layer is formed, and the silicon crystal substrate itself has gettering ability. In this method, gettering efficiency is improved by performing intrinsic gettering on a semiconductor device having a structure in which an epitaxial layer with a thickness that can be used as a defect-free layer is formed on a silicon crystal substrate with a high carbon concentration. This method is improved compared to the previous method.

〔産業上の利用分野〕[Industrial application field]

本発明はシリコン結晶基板のゲッタリング方法に係り、
特に表面にエピタキシャル層が形成されているシリコン
結晶基板(半導体装置)に対して、効率良くイントリン
シックゲッタリングを行なうゲッタリング方法に関する
The present invention relates to a gettering method for a silicon crystal substrate,
In particular, the present invention relates to a gettering method for efficiently performing intrinsic gettering on a silicon crystal substrate (semiconductor device) having an epitaxial layer formed on its surface.

LSI素子用基板として通常用いられているのは、引上
げ法(CZ法: Czochralski metho
d )で育成したシリコン結晶であるが、その結晶作製
時に微mながら不純物が混入しく内部起因の汚染)、ま
たその後の半導体デバイスの製造プロセス上でもシリコ
ン結晶基板が汚染する(外部起因の汚染)、、これらの
汚染は半導体デバイスの特性劣化。
The pulling method (CZ method) is commonly used as a substrate for LSI devices.
The silicon crystal grown in step d) is contaminated with minute amounts of impurities during crystal production (internal contamination), and the silicon crystal substrate is also contaminated during the subsequent semiconductor device manufacturing process (external contamination). ,,These contaminants deteriorate the characteristics of semiconductor devices.

%A造歩留りの低下といった問題をまねくため、シリコ
ン結晶基板の活性領域からそれらの汚染(不純物、結晶
欠陥)を除去、削減させ、良好な特性を得るために、従
来よりゲッタリングが行なわれている。
Gettering has traditionally been performed to remove and reduce contaminants (impurities, crystal defects) from the active region of silicon crystal substrates and obtain good characteristics, which can lead to problems such as a decrease in manufacturing yield. There is.

このゲッタリング技術の一つとして、イントリンシック
ゲッタリング(IG)が知られており、ゲッタリングの
効率の向上が要求される。。
Intrinsic gettering (IG) is known as one of these gettering techniques, and it is required to improve gettering efficiency. .

(従来の技術〕 第3図は従来のシリコン結晶基板のゲッタリング方法の
一例を示す。同図中、時刻t1においてシリコン結晶基
板の熱アニールが開始され、時刻t1からt2までの7
分間、02と1−IC2との混合ガス中において900
℃の温度で熱アニールが行なわれた後、毎分+10℃の
割合′c温度を上がしていく。
(Prior Art) FIG. 3 shows an example of a conventional gettering method for a silicon crystal substrate. In the figure, thermal annealing of the silicon crystal substrate is started at time t1,
900 min in a mixed gas of 02 and 1-IC2
After thermal annealing is performed at a temperature of 0.degree. C., the temperature is increased at a rate of +10.degree. C. per minute.

その後、S度が1100℃に達した後の時刻t3からt
4までの約30分間は、窒素(N2)ガス雰囲気中で、
温度1100℃の高温熱処理が行なわれる。
Thereafter, from time t3 after S degree reaches 1100°C to t
For about 30 minutes up to 4, in a nitrogen (N2) gas atmosphere,
High temperature heat treatment at a temperature of 1100° C. is performed.

これにより、シリコン結晶内の不純物酸素が外方拡散し
てシリコン結晶表面層に無欠陥層が形成される。
As a result, the impurity oxygen in the silicon crystal diffuses outward, and a defect-free layer is formed in the silicon crystal surface layer.

次に、時刻t4から毎分2℃の割合で熱処理の温度を徐
々に下げ、650℃に達した時刻t5からt6までの3
時間は650℃に保って低温熱処理が行なわれる。この
低温熱処理により前記無欠陥層よりも深いシリコン結晶
内部に微小欠陥領域が発生する(析出核を形成する)。
Next, from time t4, the heat treatment temperature was gradually lowered at a rate of 2°C per minute, and from time t5 to t6 when it reached 650°C.
Low-temperature heat treatment is performed while maintaining the temperature at 650°C. This low-temperature heat treatment generates microdefect regions (forms precipitation nuclei) inside the silicon crystal deeper than the defect-free layer.

次に、時刻t6から毎分2℃の割合で温度が上昇されて
いき、時刻t7で1100℃に達すると、その時刻t7
からt8までの30分間、1100℃の温度を保った状
態で高温熱処理が行なわれる。この高温熱処理は、直館
の低温熱処理で形成した微小欠陥をB雷度に成長させて
ゲッタリング能力をもたせるためのものである。
Next, the temperature is increased at a rate of 2 degrees Celsius per minute from time t6, and when it reaches 1100 degrees Celsius at time t7, that time t7
For 30 minutes from t8 to t8, high-temperature heat treatment is performed while maintaining the temperature at 1100°C. This high-temperature heat treatment is intended to grow the minute defects formed by the low-temperature heat treatment of Nakedate to a B-magnification degree and provide gettering ability.

しかる後に、時刻t8より毎分4℃の割合で温度が低下
され、900℃に達した時刻t9で熱処理が終了する(
アニール装置よりシリコン結晶基板が取り出される)。
After that, the temperature is lowered at a rate of 4°C per minute from time t8, and the heat treatment ends at time t9 when it reaches 900°C (
(The silicon crystal substrate is taken out from the annealing device.)

上記の時刻t3からt9までの熱処理は、酸化膜を作ら
ないように、非酸化性雰囲気中(ここではN2ガス中)
で行なわれる。
The heat treatment from time t3 to t9 above was performed in a non-oxidizing atmosphere (in N2 gas here) to avoid forming an oxide film.
It will be held in

このようなイントリンシックゲッタリングにより、シリ
コン結晶内部に微小欠陥が作製され、シリコン結晶基板
自体にゲッタリング能力がもたせられる。従って、シリ
コン結晶基板内部の微小欠陥領域にブックリングするた
め、シリコン結晶基板表面の素子活性領域は無欠陥に保
たなければならない。
By such intrinsic gettering, minute defects are created inside the silicon crystal, and the silicon crystal substrate itself is given gettering ability. Therefore, in order to book into the minute defect region inside the silicon crystal substrate, the device active region on the surface of the silicon crystal substrate must be kept defect-free.

そこで、従来シリコン結晶基板表面の素子活性領域をよ
り無欠陥に保つため、第4図の断面図に示すように、シ
リコン結晶基板1の表面に、厚さ1μm〜2μmのエピ
タキシャル層2を形成した基板に対して、第3図と同様
のイントリンシックゲッタリング熱処理を施す方法も知
られている。
Conventionally, in order to keep the device active region on the surface of a silicon crystal substrate more defect-free, an epitaxial layer 2 with a thickness of 1 μm to 2 μm was formed on the surface of a silicon crystal substrate 1, as shown in the cross-sectional view of FIG. A method of subjecting a substrate to an intrinsic gettering heat treatment similar to that shown in FIG. 3 is also known.

第4図中、シリコン結晶基板1は引上げ法で育成され、
かつ、炭素濃度が0.1ppHa以下、酸素濃度が30
 ppm1a程度の、低炭sm度引上げシリコン結晶で
ある。
In FIG. 4, a silicon crystal substrate 1 is grown by a pulling method,
and the carbon concentration is 0.1 ppHa or less and the oxygen concentration is 30
It is a pulled silicon crystal with a low carbon sm degree of about ppm 1a.

この従来方法によれば、基板3の素子活性領域には、シ
リコン結晶基板1に比べて欠陥の少ないエピタキシャル
層2が用いられており、また外部起因及び内部起因のエ
ピタキシャル層汚染がシリコン結晶基板1内部のゲッタ
リング作用で低減される。
According to this conventional method, the epitaxial layer 2 with fewer defects than the silicon crystal substrate 1 is used in the element active region of the substrate 3, and the epitaxial layer contamination caused by external and internal causes is prevented from forming on the silicon crystal substrate 1. It is reduced by internal gettering action.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前記した従来のゲッタリング方法は、いずれも
ゲッタリング作用に必要な不純物酸素の析出が十分でな
い。もし、十分な析出を得ようとすると、そのゲッタリ
ング熱処理が長時間必要になり、あるいはよりiII温
の熱処理が必要となる。
However, in the conventional gettering methods described above, the impurity oxygen necessary for the gettering action is not sufficiently precipitated. If sufficient precipitation is to be obtained, the gettering heat treatment will take a long time, or a heat treatment at a higher temperature than III will be required.

そして、この長時間で高温の熱処理のために、シリコン
結晶基板中のドーパント(リンやほう素)がその表面付
近又は第4図のエピタキシャル1112にまではい上が
ってきてしまうという問題点があった。
Due to this long-time and high-temperature heat treatment, there was a problem in that dopants (phosphorous and boron) in the silicon crystal substrate crawled up near the surface or into the epitaxial layer 1112 in FIG. 4.

本発明は上記の点に鑑みて創作されたもので、ゲッタリ
ング効率を向上することができるシリコン結晶基板のゲ
ッタリング方法を提供することを目的とする。
The present invention was created in view of the above points, and an object of the present invention is to provide a gettering method for a silicon crystal substrate that can improve gettering efficiency.

C問題点を解決するための手段〕 本発明のシリコン結晶基板のゲッタリング方法は、炭素
を0.5〜15ρpla程度含む高炭素濃度の引上げシ
リコン結晶の表面に、シリコンのエピタキシャル層が5
〜50μm程度の膜厚で形成されてなる結晶基板に対し
て、シリコン結晶内部に微小欠陥領域を形成するための
第1の熱処理と第1の熱処理の温度より高温で第2の熱
処理とを順次に行なうものである。
Means for Solving Problem C] The gettering method for a silicon crystal substrate of the present invention includes forming an epitaxial layer of silicon on the surface of a pulled silicon crystal with a high carbon concentration containing approximately 0.5 to 15 ρ pla of carbon.
A crystal substrate formed with a film thickness of ~50 μm is sequentially subjected to a first heat treatment to form a microdefect region inside the silicon crystal and a second heat treatment at a higher temperature than the first heat treatment. It is something that is done.

〔作用〕[Effect]

不純物酸素濃度が20〜30 ppma程度である引上
げ法シリコン結晶においては、もし炭素が不純物として
含まれていると、その炭素が不純物酸素析出の際の析出
核となって析出を助長する効果があるということが知ら
れている。
In a pulled silicon crystal with an impurity oxygen concentration of about 20 to 30 ppma, if carbon is included as an impurity, the carbon becomes a precipitation nucleus during impurity oxygen precipitation and has the effect of promoting precipitation. It is known that.

これは炭素原子の共有結合半径がシリコンのそれよりも
30%〜40%小さく、従って置換型不純物原子である
炭素の周りにおいては、シリコンの結晶格子は完全結晶
の場合にくらべて、大きな隙間ができた(シリコンの原
子間距離が長くなった)状態になり、そこに不純物酸素
が集り易く、かつ析出の反応(格子間シリコンの放出)
が起こり易くなる、ということによると考えられる。
This is because the covalent bond radius of carbon atoms is 30% to 40% smaller than that of silicon, and therefore the crystal lattice of silicon has larger gaps around carbon, which is a substitutional impurity atom, than in the case of a perfect crystal. (the distance between silicon atoms has become longer), impurity oxygen is likely to collect there, and a precipitation reaction (release of interstitial silicon)
This is thought to be due to the fact that it becomes more likely to occur.

事実、酸素濃度(301)l)ma程度)は同じである
が、炭素濃度が異なる2種類の引上げシリコン結晶につ
いて、前記第1の熱処理として750℃、64時間の核
形成アニールを行なった後に、前記第2の熱処理として
1000℃の核成長アニールを行なってみると、通常の
低炭素濃度(1ppma以下)のシリコン結晶において
64時間の核成長アニールで得られる酸素析出間は、高
炭素濃度(5〜7ppma )のシリコン結晶では2時
間の核成長アニールで得ることができる、ということが
知られている。
In fact, two types of pulled silicon crystals with the same oxygen concentration (about (301) l) ma) but different carbon concentrations were subjected to nucleation annealing at 750° C. for 64 hours as the first heat treatment, and then When performing a nucleus growth annealing at 1000°C as the second heat treatment, it was found that the period of oxygen precipitation obtained by 64 hours of nucleus growth annealing in a silicon crystal with a normal low carbon concentration (1 ppma or less) was at a high carbon concentration (5 ppma or less). It is known that a silicon crystal of ~7 ppma) can be obtained by 2 hours of nuclear growth annealing.

このように、引上げシリコン結晶の炭素濃度を高くする
と、不純物酸素の析出を助長することができるが、あま
り高くするとシリコン基板の結晶性を低下させてしまう
ので、一定値以上高濃度にすることはできない。
In this way, increasing the carbon concentration in the pulled silicon crystal can promote the precipitation of impurity oxygen, but if it is too high, it will reduce the crystallinity of the silicon substrate, so it is not recommended to increase the concentration above a certain value. Can not.

そこで、本発明ではシリコン結晶は炭素を0.5〜15
p1)la程度含む高炭素濃度に選定される。
Therefore, in the present invention, the silicon crystal contains 0.5 to 15 carbon atoms.
p1) Selected to have a high carbon concentration containing about la.

また、シリコン結晶にくらべて欠陥の少ないシリコンの
エピタキシャル層が、シリコン結晶の表面に、無欠陥層
として代用することができるよう、厚さが5〜50μm
程度と厚く形成される。従って、シリコン結晶基板表面
の素子活性領域の無欠陥層を形成するための、不純物酸
素の外方拡散のための熱処理が不要となる。
In addition, the thickness of the silicon epitaxial layer, which has fewer defects than silicon crystal, is 5 to 50 μm so that it can be used as a defect-free layer on the surface of the silicon crystal.
It is formed to a certain extent and thickly. Therefore, heat treatment for outward diffusion of impurity oxygen to form a defect-free layer in the element active region on the surface of the silicon crystal substrate is unnecessary.

〔実施例〕〔Example〕

第1図は本発明方法の一実施例の説明図である。 FIG. 1 is an explanatory diagram of an embodiment of the method of the present invention.

本実施例において、ゲッタリングするシリコン結晶基板
は、第2図に示す如き断面構造とされている。第2図に
おいて、シリコン結晶基板5は、直径4インチの円盤状
の引上げシリコン結晶6と、そのシリコン結晶6の表面
に、エピタキシャル法によって形成されたシリコンのエ
ピタキシャル層7とからなる。
In this embodiment, the silicon crystal substrate to be gettered has a cross-sectional structure as shown in FIG. In FIG. 2, a silicon crystal substrate 5 consists of a pulled silicon crystal 6 in the shape of a disk with a diameter of 4 inches, and a silicon epitaxial layer 7 formed on the surface of the silicon crystal 6 by an epitaxial method.

シリコン結晶6は、炭素濃度が7〜1Qppma。The silicon crystal 6 has a carbon concentration of 7 to 1 Qppma.

酸素濃度30 ppmaの高炭素濃度シリコン結晶であ
る。また、エピタキシャル層7は、厚さが10〜15μ
−と厚く選定されており、これにより表面無欠陥層とし
て用いることができる1゜この第2図の構造のシリコン
結晶基板5に対して、第1図に示す如く、時刻taより
tbまでの3時間、N2ガス雰囲気中で、750℃の温
度で熱アニール(低温熱処理)が行なわれる。この低温
熱処理によって、シリコン結晶6の内部に微小欠陥領域
が形成される。
It is a high carbon concentration silicon crystal with an oxygen concentration of 30 ppma. Further, the epitaxial layer 7 has a thickness of 10 to 15 μm.
As shown in FIG. 1, for the silicon crystal substrate 5 having the structure shown in FIG. Thermal annealing (low-temperature heat treatment) is performed at a temperature of 750° C. for an hour in an N2 gas atmosphere. By this low-temperature heat treatment, microdefect regions are formed inside the silicon crystal 6.

次に、第1図に示す如く、時刻tbより毎分5℃の割合
で温度を徐々に上昇し、1000’Cに達した時刻tc
より時刻tdまでの4時間は、温度を1000℃に保っ
てN2ガス雰囲気中で熱アニール(高温熱処理)が行な
われる。この高温熱処理によって、シリコン結晶6の内
部の微小欠陥が成長され、高密度の微小欠陥領域がf刺
される。
Next, as shown in Fig. 1, the temperature is gradually increased at a rate of 5°C per minute from time tb, and at time tc when it reaches 1000'C.
For four hours until time td, thermal annealing (high-temperature heat treatment) is performed in an N2 gas atmosphere while keeping the temperature at 1000°C. By this high-temperature heat treatment, minute defects inside the silicon crystal 6 grow, and a high-density minute defect region is pierced.

次に、上記の時刻tdより毎分4℃の割合で温度を低下
していき、850℃に達した時刻[eで、シリコン結晶
基板5の熱アニールを終了する。
Next, the temperature is lowered at a rate of 4° C. per minute from time td, and at time e when it reaches 850° C., the thermal annealing of the silicon crystal substrate 5 is completed.

このように、本実施例によれば、従来必要であった酸素
の外方拡散のための熱処理1稈をすべて省略でき、微小
欠陥領域形成及び成長のための熱処理だけでよく、第1
図に示す如く総処理時間は8時間30分であり、第3図
に示した従来方法の総処理時間13詩間30分にくらべ
、短時間でゲッタリングができる。
As described above, according to this embodiment, the heat treatment for outward diffusion of oxygen, which was conventionally necessary, can be omitted, and only the heat treatment for the formation and growth of micro-defect regions is required.
As shown in the figure, the total processing time is 8 hours and 30 minutes, and compared to the conventional method shown in FIG. 3, which takes a total processing time of 13 minutes and 30 minutes, gettering can be accomplished in a shorter time.

また、本実施例のR高温度は1000℃であり、前記従
来方法の最高温度1100℃にくらべ、低温度でよく、
シリコン結晶6からエピタキシャル層7へのドーパント
のはい上がりを低減することができる。
Further, the R high temperature in this example is 1000°C, which is lower than the maximum temperature of 1100°C in the conventional method.
The creeping up of dopants from silicon crystal 6 to epitaxial layer 7 can be reduced.

(発明の効果) 上述の如く、本発明によれば、高炭素S度の引上げシリ
コン結晶を用いて、不純物酸木の析出を助長するように
したので、従来に比べて短時間で(又は低温で)同等の
酸素析出mを得ることができる。また、シリコン結晶の
表面に、無欠陥層となるエピタキシャル層を形成し、基
板表面に無欠陥層を形成するための熱処理を不要とした
ので、シリコン結晶内部に高密度微小欠陥領域を形成す
るための熱処理を行なうだけでよく、総熱処理時間を従
来にくらべて大幅に短縮でき、このことからシリコン結
晶からエピタキシャルmのドーパントのはい上がりのm
を従来にくらべて低減することができ、以上より従来に
くらべて、効率よく、イントリンシックゲッタリングを
行なうことができる等の特長を有するものである。
(Effects of the Invention) As described above, according to the present invention, a pulled silicon crystal with a high carbon S degree is used to promote the precipitation of impurity acid wood, so it can be produced in a shorter time (or at a lower temperature) than in the past. ) equivalent oxygen precipitation m can be obtained. In addition, an epitaxial layer that becomes a defect-free layer is formed on the surface of the silicon crystal, eliminating the need for heat treatment to form a defect-free layer on the substrate surface. The total heat treatment time can be significantly shortened compared to the conventional method.
The present invention has the advantage that it is possible to reduce the amount of noise compared to the conventional method, and to perform intrinsic gettering more efficiently than the conventional method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明方法の一実施例の説明図、第2図は本発
明方法においてゲッタリングされるシリコン結晶基板の
一実施例を示す縦断面図、第3図は従来方法の一例の説
明図、 第4図は従来方法においてゲッタリングされるシリコン
結晶基板の一例を示す縦断面図である。 図において、 5はシリコン結晶基板、 6は引上げシリコン結晶、 7はシリコンのエピタキシャル層である。 本発明方法の一実施例の説明図 第1図 シリコン結晶基板の一実施例の断面図 第2図
FIG. 1 is an explanatory diagram of an embodiment of the method of the present invention, FIG. 2 is a vertical cross-sectional view of an embodiment of a silicon crystal substrate to be gettered in the method of the present invention, and FIG. 3 is an explanatory diagram of an example of the conventional method. FIG. 4 is a vertical cross-sectional view showing an example of a silicon crystal substrate that is gettered in a conventional method. In the figure, 5 is a silicon crystal substrate, 6 is a pulled silicon crystal, and 7 is a silicon epitaxial layer. An explanatory diagram of an embodiment of the method of the present invention. Figure 1. A sectional view of an embodiment of a silicon crystal substrate. Figure 2.

Claims (1)

【特許請求の範囲】[Claims] 炭素を0.5〜15ppma程度含む高炭素濃度の引上
げシリコン結晶(6)の表面に、エピタキシャル成長法
によつてシリコンのエピタキシャル層(7)が5〜50
μm程度の厚さで形成されてなる結晶基板(5)に対し
て、前記シリコン結晶(6)の内部に微小欠陥領域を形
成するための第1の熱処理を行なった後、該第1の熱処
理時の温度より高温で第2の熱処理を行なうことを特徴
とするシリコン結晶基板のゲッタリング方法。
A silicon epitaxial layer (7) with a thickness of 5 to 50% is formed by an epitaxial growth method on the surface of a pulled silicon crystal (6) with a high carbon concentration containing about 0.5 to 15 ppma of carbon.
After performing a first heat treatment for forming a micro defect region inside the silicon crystal (6) on a crystal substrate (5) formed with a thickness of about μm, the first heat treatment 1. A method for gettering a silicon crystal substrate, the method comprising performing a second heat treatment at a temperature higher than the temperature at which the silicon crystal substrate is heated.
JP6181787A 1987-03-17 1987-03-17 Gettering method for silicon crystal substrate Pending JPS63227026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6181787A JPS63227026A (en) 1987-03-17 1987-03-17 Gettering method for silicon crystal substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6181787A JPS63227026A (en) 1987-03-17 1987-03-17 Gettering method for silicon crystal substrate

Publications (1)

Publication Number Publication Date
JPS63227026A true JPS63227026A (en) 1988-09-21

Family

ID=13182016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6181787A Pending JPS63227026A (en) 1987-03-17 1987-03-17 Gettering method for silicon crystal substrate

Country Status (1)

Country Link
JP (1) JPS63227026A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539245A (en) * 1991-11-18 1996-07-23 Mitsubishi Materials Silicon Corporation Semiconductor substrate having a gettering layer
WO1998005063A1 (en) * 1996-07-29 1998-02-05 Sumitomo Sitix Corporation Silicon epitaxial wafer and method for manufacturing the same
JPH10229093A (en) * 1997-02-17 1998-08-25 Sumitomo Sitix Corp Production of silicon epitaxial wafer
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JPH11204534A (en) * 1998-01-14 1999-07-30 Sumitomo Metal Ind Ltd Manufacture of silicon epitaxial wafer
US6641888B2 (en) 1999-03-26 2003-11-04 Sumitomo Mitsubishi Silicon Corporation Silicon single crystal, silicon wafer, and epitaxial wafer.
US6878451B2 (en) 1999-07-28 2005-04-12 Sumitomo Mitsubishi Silicon Corporation Silicon single crystal, silicon wafer, and epitaxial wafer
JP2009170936A (en) * 2009-04-21 2009-07-30 Sumco Corp Manufacturing method of silicon semiconductor substrate
WO2010116761A1 (en) * 2009-04-10 2010-10-14 株式会社Sumco Method for manufacturing epitaxial silicon wafer, and epitaxial silicon wafer
JP2011086706A (en) * 2009-10-14 2011-04-28 Sumco Corp Epitaxial substrate for backside illumination type solid-state image pickup element and method of manufacturing the same
JP2011086702A (en) * 2009-10-14 2011-04-28 Sumco Corp Epitaxial substrate for backside illumination type solid-state image pickup element and method of manufacturing the same
JP2011096979A (en) * 2009-11-02 2011-05-12 Sumco Corp Silicon wafer and method for producing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5982717A (en) * 1982-11-02 1984-05-12 Nec Corp Manufacture of semiconductor device
JPS5994809A (en) * 1982-11-22 1984-05-31 Fujitsu Ltd Production of semiconductor element
JPS6094722A (en) * 1983-08-16 1985-05-27 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Silicon wafer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5982717A (en) * 1982-11-02 1984-05-12 Nec Corp Manufacture of semiconductor device
JPS5994809A (en) * 1982-11-22 1984-05-31 Fujitsu Ltd Production of semiconductor element
JPS6094722A (en) * 1983-08-16 1985-05-27 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Silicon wafer

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539245A (en) * 1991-11-18 1996-07-23 Mitsubishi Materials Silicon Corporation Semiconductor substrate having a gettering layer
US6277501B1 (en) 1996-07-29 2001-08-21 Sumitomo Metal Industries, Ltd. Silicon epitaxial wafer and method for manufacturing the same
WO1998005063A1 (en) * 1996-07-29 1998-02-05 Sumitomo Sitix Corporation Silicon epitaxial wafer and method for manufacturing the same
KR100351532B1 (en) * 1996-07-29 2002-09-11 스미토모 긴조쿠 고교 가부시키가이샤 Silicon epitaxial wafer and method for manufacturing the same
JPH10229093A (en) * 1997-02-17 1998-08-25 Sumitomo Sitix Corp Production of silicon epitaxial wafer
JPH11150119A (en) * 1997-11-14 1999-06-02 Sumitomo Sitix Corp Method and device for heat-treating silicon semiconductor substance
JPH11204534A (en) * 1998-01-14 1999-07-30 Sumitomo Metal Ind Ltd Manufacture of silicon epitaxial wafer
US6641888B2 (en) 1999-03-26 2003-11-04 Sumitomo Mitsubishi Silicon Corporation Silicon single crystal, silicon wafer, and epitaxial wafer.
US6878451B2 (en) 1999-07-28 2005-04-12 Sumitomo Mitsubishi Silicon Corporation Silicon single crystal, silicon wafer, and epitaxial wafer
WO2010116761A1 (en) * 2009-04-10 2010-10-14 株式会社Sumco Method for manufacturing epitaxial silicon wafer, and epitaxial silicon wafer
JP5545293B2 (en) * 2009-04-10 2014-07-09 株式会社Sumco Epitaxial silicon wafer manufacturing method, epitaxial silicon wafer
JP2009170936A (en) * 2009-04-21 2009-07-30 Sumco Corp Manufacturing method of silicon semiconductor substrate
JP2011086706A (en) * 2009-10-14 2011-04-28 Sumco Corp Epitaxial substrate for backside illumination type solid-state image pickup element and method of manufacturing the same
JP2011086702A (en) * 2009-10-14 2011-04-28 Sumco Corp Epitaxial substrate for backside illumination type solid-state image pickup element and method of manufacturing the same
JP2011096979A (en) * 2009-11-02 2011-05-12 Sumco Corp Silicon wafer and method for producing the same

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